Abstract
Presented in this paper is a fundamental mathematical basis for determining the lower bounds on power dissipation in digital signal processing (DSP) algorithms. This basis is derived from information-theoretic arguments. In particular, a digital signal processing algorithm is viewed as a process of information transfer with an inherent information transfer rate requirement of R bits/sec. Different architectures implementing a given algorithm are equivalent to different communication networks each with a certain capacity C (also in bits/sec). The absolute lower bound on the power dissipation for any given architecture is then obtained by minimizing the signal power such that its channel capacity C is equal to the desired information transfer rate R. The proposed framework is employed to determine the lower-bounds for simple digital filters. Furthermore, lower bounds on the power dissipation achievable via adiabatic logic is also presented thus demonstrating the versatility of the proposed approach.
Original language | English (US) |
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Pages | 43-48 |
Number of pages | 6 |
State | Published - 1996 |
Event | Proceedings of the 1996 International Symposium on Low Power Electronics and Design - Monterey, CA, USA Duration: Aug 12 1996 → Aug 14 1996 |
Other
Other | Proceedings of the 1996 International Symposium on Low Power Electronics and Design |
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City | Monterey, CA, USA |
Period | 8/12/96 → 8/14/96 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials