Lower bounds on power-dissipation for DSP algorithms

Research output: Contribution to conferencePaper

Abstract

Presented in this paper is a fundamental mathematical basis for determining the lower bounds on power dissipation in digital signal processing (DSP) algorithms. This basis is derived from information-theoretic arguments. In particular, a digital signal processing algorithm is viewed as a process of information transfer with an inherent information transfer rate requirement of R bits/sec. Different architectures implementing a given algorithm are equivalent to different communication networks each with a certain capacity C (also in bits/sec). The absolute lower bound on the power dissipation for any given architecture is then obtained by minimizing the signal power such that its channel capacity C is equal to the desired information transfer rate R. The proposed framework is employed to determine the lower-bounds for simple digital filters. Furthermore, lower bounds on the power dissipation achievable via adiabatic logic is also presented thus demonstrating the versatility of the proposed approach.

Original languageEnglish (US)
Pages43-48
Number of pages6
StatePublished - Dec 1 1996
EventProceedings of the 1996 International Symposium on Low Power Electronics and Design - Monterey, CA, USA
Duration: Aug 12 1996Aug 14 1996

Other

OtherProceedings of the 1996 International Symposium on Low Power Electronics and Design
CityMonterey, CA, USA
Period8/12/968/14/96

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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    Shanbhag, N. R. (1996). Lower bounds on power-dissipation for DSP algorithms. 43-48. Paper presented at Proceedings of the 1996 International Symposium on Low Power Electronics and Design, Monterey, CA, USA, .