Abstract
Presented in this paper is a systematic methodology to design low-power integrated transceivers for broadband data communications over unshielded twisted-pair (UTP) channels. The design methodology is based upon two algorithmic low-power techniques referred to as Hilbert transformation and strength reduction and a high-speed pipelining technique referred to as relaxed look-ahead transformation. Finite-precision requirements and power savings are presented. The application of these techniques to design low-power and high-speed 155.52 Mb/s ATM-LAN and 51.84 Mb/s VDSL transceivers is illustrated.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 474-477 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 6 |
| State | Published - 1998 |
| Event | Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA Duration: May 31 1998 → Jun 3 1998 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering