Low-power VLSI decoder architectures for LDPC codes

Mohammad M. Mansour, Naresh R. Shanbhag

Research output: Contribution to conferencePaper

Abstract

Iterative decoding of low-density parity check codes (LDPC) using the message-passing algorithm have proved to be extraordinarily effective compared to conventional maximum-likelihood decoding. However, the lack of any structural regularity in these essentially random codes is a major challenge for building a practical low-power LDPC decoder. In this paper, we jointly design the code and the decoder to induce the structural regularity needed for a reduced-complexity parallel decoder architecture. This interconnect-driven code design approach eliminates the need for a complex interconnection network while still retaining the algorithmic performance promised by random codes. Moreover, we propose a new approach for computing reliability metrics based on the BCJR algorithm that reduces the message switching activity in the decoder compared to existing approaches. Simulations show that the proposed approach results in power savings of up to 85.64% over conventional implementations.

Original languageEnglish (US)
Pages284-289
Number of pages6
DOIs
StatePublished - Jan 1 2002
EventProceedings of the 2002 International Symposium on Low Power Electronics and Design - Monterey, CA, United States
Duration: Aug 12 2002Aug 14 2002

Other

OtherProceedings of the 2002 International Symposium on Low Power Electronics and Design
CountryUnited States
CityMonterey, CA
Period8/12/028/14/02

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Keywords

  • BCJR algorithm
  • LDPC codes
  • Lower power architectures

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Mansour, M. M., & Shanbhag, N. R. (2002). Low-power VLSI decoder architectures for LDPC codes. 284-289. Paper presented at Proceedings of the 2002 International Symposium on Low Power Electronics and Design, Monterey, CA, United States. https://doi.org/10.1109/lpe.2002.146756