Abstract
In this paper, we propose a low complexity architecture for turbo equalizers. Turbo equalizers jointly equalize and decode the received signal by exchanging soft information iteratively. The proposed architecture employs early termination of the iterative process when it does not impact the bit-error rate (BER). Early termination enables the powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power. Simulation results show that the complexity is reduced by 20% ∼ 59% and 8% ∼ 58% in equalization and decoding, respectively. In addition, the number of iterations is reduced by 30% ∼ 47% with negligible degradation in BER.
| Original language | English (US) |
|---|---|
| Title of host publication | IEEE Workshop on Signal Processing Systems, SiPS |
| Subtitle of host publication | Design and Implementation |
| Pages | 33-38 |
| Number of pages | 6 |
| ISBN (Electronic) | 0780375874 |
| DOIs | |
| State | Published - 2002 |
Keywords
- Binary phase shift keying
- Bit error rate
- DSL
- Decision feedback equalizers
- Degradation
- Design optimization
- Frequency
- Intersymbol interference
- Iterative decoding
- Termination of employment
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Signal Processing
- Applied Mathematics
- Hardware and Architecture