Abstract

In this paper, we propose a low complexity architecture for turbo equalizers. Turbo equalizers jointly equalize and decode the received signal by exchanging soft information iteratively. The proposed architecture employs early termination of the iterative process when it does not impact the bit-error rate (BER). Early termination enables the powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power. Simulation results show that the complexity is reduced by 20% ∼ 59% and 8% ∼ 58% in equalization and decoding, respectively. In addition, the number of iterations is reduced by 30% ∼ 47% with negligible degradation in BER.

Original languageEnglish (US)
Title of host publicationIEEE Workshop on Signal Processing Systems, SiPS
Subtitle of host publicationDesign and Implementation
Pages33-38
Number of pages6
ISBN (Electronic)0780375874
DOIs
StatePublished - Jan 1 2002

Fingerprint

Equalizer
Equalizers
Early Termination
Bit error rate
Error Rate
Power Saving
Decode
Equalization
Iterative Process
Low Complexity
Decoding
Degradation
Iteration
Output
Architecture
Simulation

Keywords

  • Binary phase shift keying
  • Bit error rate
  • DSL
  • Decision feedback equalizers
  • Degradation
  • Design optimization
  • Frequency
  • Intersymbol interference
  • Iterative decoding
  • Termination of employment

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Applied Mathematics
  • Hardware and Architecture

Cite this

Lee, S. J., Shanbhag, N. R., & Singer, A. C. (2002). Low-power turbo equalizer architecture. In IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation (pp. 33-38). [1049681] https://doi.org/10.1109/SIPS.2002.1049681

Low-power turbo equalizer architecture. / Lee, Seok Jun; Shanbhag, N. R.; Singer, A. C.

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. 2002. p. 33-38 1049681.

Research output: Chapter in Book/Report/Conference proceedingChapter

Lee, SJ, Shanbhag, NR & Singer, AC 2002, Low-power turbo equalizer architecture. in IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation., 1049681, pp. 33-38. https://doi.org/10.1109/SIPS.2002.1049681
Lee SJ, Shanbhag NR, Singer AC. Low-power turbo equalizer architecture. In IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. 2002. p. 33-38. 1049681 https://doi.org/10.1109/SIPS.2002.1049681
Lee, Seok Jun ; Shanbhag, N. R. ; Singer, A. C. / Low-power turbo equalizer architecture. IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. 2002. pp. 33-38
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