Low-power technology mapping for FPGA architectures with dual supply voltages

Deming Chen, Jason Cong, Fei Li, Lei He

Research output: Contribution to conferencePaper

Abstract

In this paper we study the technology mapping problem of FPGA architectures with dual supply voltages (Vdds) for power optimization. This is done with the guarantee that the mapping depth of the circuit will not increase compared to the circuit with a single Vdd. We first design a single-Vdd mapping algorithm that achieves better power results than the latest published low-power mapping algorithms. We then show that our dual-Vdd mapping algorithm can further improve power savings by up to 11.6% over the single-Vdd mapper. In addition, we investigate the best low-Vdd/high-Vdd ratio for the largest power reduction among several dual-Vdd combinations. To our knowledge, this is the first work on dual-Vdd mapping for FPGA architectures.

Original languageEnglish (US)
Pages109-117
Number of pages9
DOIs
StatePublished - Jan 1 2004
EventACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays - FPGA 2004 - Monterey, CA., United States
Duration: Feb 22 2004Feb 24 2004

Other

OtherACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays - FPGA 2004
CountryUnited States
CityMonterey, CA.
Period2/22/042/24/04

Keywords

  • Dual supply voltage
  • Low-power FPGA
  • Technology mapping

ASJC Scopus subject areas

  • Computer Science(all)

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  • Cite this

    Chen, D., Cong, J., Li, F., & He, L. (2004). Low-power technology mapping for FPGA architectures with dual supply voltages. 109-117. Paper presented at ACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays - FPGA 2004, Monterey, CA., United States. https://doi.org/10.1145/968280.968297