Abstract
In this paper we study the technology mapping problem of FPGA architectures with dual supply voltages (Vdds) for power optimization. This is done with the guarantee that the mapping depth of the circuit will not increase compared to the circuit with a single Vdd. We first design a single-Vdd mapping algorithm that achieves better power results than the latest published low-power mapping algorithms. We then show that our dual-Vdd mapping algorithm can further improve power savings by up to 11.6% over the single-Vdd mapper. In addition, we investigate the best low-Vdd/high-Vdd ratio for the largest power reduction among several dual-Vdd combinations. To our knowledge, this is the first work on dual-Vdd mapping for FPGA architectures.
Original language | English (US) |
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Pages | 109-117 |
Number of pages | 9 |
DOIs | |
State | Published - 2004 |
Externally published | Yes |
Event | ACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays - FPGA 2004 - Monterey, CA., United States Duration: Feb 22 2004 → Feb 24 2004 |
Other
Other | ACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays - FPGA 2004 |
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Country/Territory | United States |
City | Monterey, CA. |
Period | 2/22/04 → 2/24/04 |
Keywords
- Dual supply voltage
- Low-power FPGA
- Technology mapping
ASJC Scopus subject areas
- General Computer Science