TY - JOUR
T1 - Low-power supply-regulation techniques for ring oscillators in phase-locked loops using a split-tuned architecture
AU - Arakali, Abhijith
AU - Gondi, Srikanth
AU - Hanumolu, Pavan Kumar
N1 - Funding Information:
Manuscript received December 01, 2008; revised April 20, 2009. Current version published July 22, 2009. This work was supported in part by Semiconductor Research Corporation under Contract 2007-HJ-1597. A. Arakali and P. K. Hanumolu are with the School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR 97331 USA (e-mail: [email protected]). S. Gondi is with Kawasaki Microelectronics America, Inc., R&D Division, San Jose, CA 95131 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2009.2022916
PY - 2009/8
Y1 - 2009/8
N2 - A supply-regulated phase-locked loop (PLL) employs a split-tuned architecture to decouple the tradeoff between supply-noise rejection performance and power consumption. By placing the regulator in the low-bandwidth coarse loop, the proposed PLL architecture allows us to maximize its bandwidth to suppress the oscillator phase noise with neither the power supply-noise rejection nor the power dissipation of the regulator being affected. A replica-based regulator introduces a low-frequency pole in its supply-noise transfer function and avoids degradation of supply-noise rejection beyond the regulator-loop's dominant pole frequency. The prototype PLL fabricated in a 0.18 μm digital CMOS process operates from 0.5 to 2.5 GHz. At 1.5 GHz, the proposed PLL achieves 1.9 ps long-term rms jitter and a worst case supply-noise sensitivity of -28 dB (0.5 rad/V), an improvement of 20 dB over conventional solutions, while consuming 2.2 mA from a 1.8 V supply.
AB - A supply-regulated phase-locked loop (PLL) employs a split-tuned architecture to decouple the tradeoff between supply-noise rejection performance and power consumption. By placing the regulator in the low-bandwidth coarse loop, the proposed PLL architecture allows us to maximize its bandwidth to suppress the oscillator phase noise with neither the power supply-noise rejection nor the power dissipation of the regulator being affected. A replica-based regulator introduces a low-frequency pole in its supply-noise transfer function and avoids degradation of supply-noise rejection beyond the regulator-loop's dominant pole frequency. The prototype PLL fabricated in a 0.18 μm digital CMOS process operates from 0.5 to 2.5 GHz. At 1.5 GHz, the proposed PLL achieves 1.9 ps long-term rms jitter and a worst case supply-noise sensitivity of -28 dB (0.5 rad/V), an improvement of 20 dB over conventional solutions, while consuming 2.2 mA from a 1.8 V supply.
KW - Phase-locked loop
KW - Ring oscillator
KW - Split-tunning
KW - Supply-noise sensitivity
KW - Voltage regulator
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U2 - 10.1109/JSSC.2009.2022916
DO - 10.1109/JSSC.2009.2022916
M3 - Article
AN - SCOPUS:68549101796
SN - 0018-9200
VL - 44
SP - 2169
EP - 2180
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 8
M1 - 5173751
ER -