@inproceedings{75becdbdaf2d40529d86995564b72421,
title = "Low-power pre-decoding based viterbi decoder for tail-biting convolutional codes",
abstract = "Low-power and high-throughput Viterbi decoder (VD) for tail-biting convolutional codes is presented in this paper. First, a low complexity radix-4 VD with enhanced decoding features such as end-state forcing and best-state trace back is presented. Second, simple predecoding is proposed to decrease the runtime of VD, resulting in significant power saving. The design is implemented in 0.9 V TI 45-nm CMOS process at 100 MHz for Long Term Evolution (LTE) [1] as application. More than 90% power saving is achieved with predecoding at a throughput of 120 Mbps and 0.2 dB SNR loss for 10-5 frame error rate.",
keywords = "Add-compare-select, Long term evolution, Tail-biting convolutional code, Trellis decoding, Viterbi decoder",
author = "Abdallah, {Rami A.} and Lee, {Seok Jun} and Manish Goel and Shanbhag, {Naresh R}",
year = "2009",
doi = "10.1109/SIPS.2009.5336249",
language = "English (US)",
isbn = "9781424443352",
series = "IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation",
pages = "185--190",
booktitle = "2009 IEEE Workshop on Signal Processing Systems, SiPS 2009 - Proceedings",
note = "2009 IEEE Workshop on Signal Processing Systems, SiPS 2009 ; Conference date: 07-10-2009 Through 09-10-2009",
}