Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard

Junho Cho; Naresh R. Shanbhag; Wonyong Sung

doi:10.1109/SIPS.2009.5336223

Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard

Junho Cho, Naresh R. Shanbhag, Wonyong Sung

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Flexible and scalable LDPC decoder architecture is developed for the IEEE 802.11n standard. The serial-parallel architecture is employed for achieving high throughput with low chip area, and triple-bank memory blocks are used for parallel factor expansion. Two low-power strategies using voltage over-scaling (VaS) and reduced-precision replica (RPR) are applied to the decoder. By applying these techniques, power saving of up to 35% is demonstrated when implemented in a 90nm CMOS technology.

Original language	English (US)
Title of host publication	2009 IEEE Workshop on Signal Processing Systems, SiPS 2009 - Proceedings
Pages	40-45
Number of pages	6
DOIs	https://doi.org/10.1109/SIPS.2009.5336223
State	Published - 2009
Event	2009 IEEE Workshop on Signal Processing Systems, SiPS 2009 - Tampere, Finland Duration: Oct 7 2009 → Oct 9 2009

Publication series

Name	IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)	1520-6130

Other

Other	2009 IEEE Workshop on Signal Processing Systems, SiPS 2009
Country/Territory	Finland
City	Tampere
Period	10/7/09 → 10/9/09

ASJC Scopus subject areas

Electrical and Electronic Engineering
Signal Processing
Applied Mathematics
Hardware and Architecture

Online availability

10.1109/SIPS.2009.5336223

Library availability

Discover UIUC Full Text

Cite this

Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard. / Cho, Junho; Shanbhag, Naresh R.; Sung, Wonyong.
2009 IEEE Workshop on Signal Processing Systems, SiPS 2009 - Proceedings. 2009. p. 40-45 5336223 (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Cho, J, Shanbhag, NR & Sung, W 2009, Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard. in 2009 IEEE Workshop on Signal Processing Systems, SiPS 2009 - Proceedings., 5336223, IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, pp. 40-45, 2009 IEEE Workshop on Signal Processing Systems, SiPS 2009, Tampere, Finland, 10/7/09. https://doi.org/10.1109/SIPS.2009.5336223

@inproceedings{8a41d5747f5f4062b69a0a0f90db318d,

title = "Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard",

abstract = "Flexible and scalable LDPC decoder architecture is developed for the IEEE 802.11n standard. The serial-parallel architecture is employed for achieving high throughput with low chip area, and triple-bank memory blocks are used for parallel factor expansion. Two low-power strategies using voltage over-scaling (VaS) and reduced-precision replica (RPR) are applied to the decoder. By applying these techniques, power saving of up to 35% is demonstrated when implemented in a 90nm CMOS technology.",

author = "Junho Cho and Shanbhag, {Naresh R.} and Wonyong Sung",

year = "2009",

doi = "10.1109/SIPS.2009.5336223",

language = "English (US)",

isbn = "9781424443352",

series = "IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation",

pages = "40--45",

booktitle = "2009 IEEE Workshop on Signal Processing Systems, SiPS 2009 - Proceedings",

}

TY - GEN

T1 - Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard

AU - Cho, Junho

AU - Shanbhag, Naresh R.

AU - Sung, Wonyong

PY - 2009

Y1 - 2009

N2 - Flexible and scalable LDPC decoder architecture is developed for the IEEE 802.11n standard. The serial-parallel architecture is employed for achieving high throughput with low chip area, and triple-bank memory blocks are used for parallel factor expansion. Two low-power strategies using voltage over-scaling (VaS) and reduced-precision replica (RPR) are applied to the decoder. By applying these techniques, power saving of up to 35% is demonstrated when implemented in a 90nm CMOS technology.

AB - Flexible and scalable LDPC decoder architecture is developed for the IEEE 802.11n standard. The serial-parallel architecture is employed for achieving high throughput with low chip area, and triple-bank memory blocks are used for parallel factor expansion. Two low-power strategies using voltage over-scaling (VaS) and reduced-precision replica (RPR) are applied to the decoder. By applying these techniques, power saving of up to 35% is demonstrated when implemented in a 90nm CMOS technology.

UR - http://www.scopus.com/inward/record.url?scp=74549139694&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=74549139694&partnerID=8YFLogxK

U2 - 10.1109/SIPS.2009.5336223

DO - 10.1109/SIPS.2009.5336223

M3 - Conference contribution

AN - SCOPUS:74549139694

SN - 9781424443352

T3 - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

SP - 40

EP - 45

BT - 2009 IEEE Workshop on Signal Processing Systems, SiPS 2009 - Proceedings

T2 - 2009 IEEE Workshop on Signal Processing Systems, SiPS 2009

Y2 - 7 October 2009 through 9 October 2009

ER -

Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard

Abstract

Publication series

Other

ASJC Scopus subject areas

Online availability

Library availability

Related links

Fingerprint

Cite this