Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard

Junho Cho, Naresh R. Shanbhag, Wonyong Sung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Flexible and scalable LDPC decoder architecture is developed for the IEEE 802.11n standard. The serial-parallel architecture is employed for achieving high throughput with low chip area, and triple-bank memory blocks are used for parallel factor expansion. Two low-power strategies using voltage over-scaling (VaS) and reduced-precision replica (RPR) are applied to the decoder. By applying these techniques, power saving of up to 35% is demonstrated when implemented in a 90nm CMOS technology.

Original languageEnglish (US)
Title of host publication2009 IEEE Workshop on Signal Processing Systems, SiPS 2009 - Proceedings
Pages40-45
Number of pages6
DOIs
StatePublished - 2009
Externally publishedYes
Event2009 IEEE Workshop on Signal Processing Systems, SiPS 2009 - Tampere, Finland
Duration: Oct 7 2009Oct 9 2009

Publication series

NameIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)1520-6130

Other

Other2009 IEEE Workshop on Signal Processing Systems, SiPS 2009
Country/TerritoryFinland
CityTampere
Period10/7/0910/9/09

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Applied Mathematics
  • Hardware and Architecture

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