Low-Power High-Level Synthesis for FPGA Architectures

Keyphrases

• Low Power 100%
• Energy Consumption Reduction 100%
• High-level Synthesis 100%
• Power Estimator 100%
• FPGA Architecture 100%
• Path Generation 50%
• Simulated Annealing 50%
• Estimation Error 50%
• Static Power 50%
• Dynamic Power 50%
• Register Data 50%
• Matching Algorithm 50%
• Compiler 50%
• Function Unit 50%
• Synopsys 50%
• Power Estimation 50%
• Register Binding 50%
• Synthesis System 50%
• Low-power Design 50%
• FPGA Circuit 50%
• FPGA Design 50%
• Wirelength 50%
• Weighted Bipartite Matching 50%
• FPGA Component 50%
• Resource Selection Function 50%

Computer Science

• High Level Synthesis 100%
• Field Programmable Gate Arrays 100%
• Experimental Result 20%
• Estimation Error 20%
• Matching Algorithm 20%
• Power Consumption 20%
• Selection Function 20%
• Simulated Annealing 20%
• Register Binding 20%
• Dynamic Power 20%
• Low-Power Design 20%
• Reduce Power Consumption 20%
• bipartite matching 20%
• Static Power 20%