Low-power FFT via reduced precision redundancy

S. R. Sridhara, Naresh R Shanbhag

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we propose a technique for designing low-power fast Fourier transform (FFT) processors with applications in next generation wireless LAN and wireless access systems. The proposed low-power technique is based on the general principle of soft digital signal processing [4] where voltage overscaling (VOS) [4] (scaling the supply voltage beyond the critical voltage Vdd-crit required for correct operation) is applied in conjunction with algorithm noise-tolerance (ANT) techniques. In this paper, we propose an ANT technique referred to as reduced precision redundancy for compensating the degradation in the signal-to-noise ratio (SNR) at an FFT output due to VOS. Simulation results using the proposed scheme with 0.25 μm standard CMOS technology show that the power consumption in a butterfly functional unit of an FFT processor can be reduced by 44% over a conventional voltage-scaled system without any SNR loss in the context of a typical orthogonal frequency division multiplexing (OFDM) based WLAN system.

Original languageEnglish (US)
Title of host publicationIEEE Workshop on Signal Processing Systems, SiPS
Subtitle of host publicationDesign and Implementation
EditorsF. Catthoor, M. Moonen
Pages117-124
Number of pages8
StatePublished - 2001
EventIEEE Workshop on Signal Processing Systems- Design and Implementation-(SIPS) 2001 - Antwerp, Belgium
Duration: Oct 26 2001Oct 28 2001

Other

OtherIEEE Workshop on Signal Processing Systems- Design and Implementation-(SIPS) 2001
Country/TerritoryBelgium
CityAntwerp
Period10/26/0110/28/01

ASJC Scopus subject areas

  • Signal Processing
  • Media Technology

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