Low-power equalizers for 51.84 Mb/s very high-speed digital subscriber loop (VDSL) modems

Manish Goel, Naresh R. Shanbhag

Research output: Contribution to conferencePaperpeer-review

Abstract

In this paper, we present low-power equalizers derived via dynamic algorithm transformations (DAT). These transformations achieve low-energy operation by reconfiguring the architecture and the supply voltage in response to channel non-stationarities. Practical reconfiguration strategies are derived as a solution to an optimization problem with energy as the objective function and a constraint on the algorithm performance (specifically the SNR). Simple energy models for multipliers are presented. The DAT-based adaptive filter is employed as an equalizer for 51.84 Mb/s very high-speed digital subscriber loop (VDSL) over 24-pair BKMA cable. On the average, 88% energy savings are achieved due to variations in cable length and number of far-end crosstalk (FEXT) interferers.

Original languageEnglish (US)
Pages317-326
Number of pages10
StatePublished - 1998
EventProceedings of the 1998 IEEE Workshop on Signal Processing Systems, SIPS - Cambridge, MA, USA
Duration: Oct 8 1998Oct 10 1998

Other

OtherProceedings of the 1998 IEEE Workshop on Signal Processing Systems, SIPS
CityCambridge, MA, USA
Period10/8/9810/10/98

ASJC Scopus subject areas

  • Signal Processing
  • Media Technology

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