Abstract
In this paper, we present a low-power Distributed Arithmetic (DA) architecture. In a DA architecture, a memory is employed to store linear combinations of coefficients. The probability distribution of addresses to the memory is usually not uniform because of temporal correlation in the input. We present a rule governing this probability distribution and use it to partition the memory such that the most frequently accessed locations are stored in the smallest memory. Power dissipation is reduced because accesses to smaller memories dissipate less power. Experimental results with an 8-tap filter with 8 bits of data precision result in a 32% power reduction in the memory. A 28% power reduction was obtained by just detecting accesses to the two most frequently accessed locations (0×00 and 0×FF), which is a strong argument for using the techniques proposed in this paper.
| Original language | English (US) |
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| Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
| Publisher | IEEE |
| Volume | 3 |
| ISBN (Print) | 0780354710 |
| State | Published - 1999 |
| Event | Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 - Orlando, FL, USA Duration: May 30 1999 → Jun 2 1999 |
Other
| Other | Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 |
|---|---|
| City | Orlando, FL, USA |
| Period | 5/30/99 → 6/2/99 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials