Low-power digital signal processing via dynamic algorithm transformations (DAT)

We have proposed dynamic algorithm transformations (DAT) for low power VLSI signal processing. The principle behind DAT is that the conventional signal processing system designed for the worst-case is not optimum (from energy viewpoint) for the nominal and the best cases. Therefore, significant energy savings can be achieved by optimally reconfiguring the hardware in these situations. The reconfiguration strategies are derived by solving an optimization problem with energy as the objective function, and a constraint on the SNR. In this paper, we present reconfiguration strategies for a system comprising of multiple adaptive filters. An example is 155.52 Mb/s ATM-LAN transceiver, where two adaptive filters - namely near-end crosstalk canceller and fractionally spaced equalizer are employed. The input variabilities for this example are due to the different cable lengths at various locations. Simulation results indicate that energy savings range from 0%-85% for cable lengths ranging from 110 m to 40 m. On an average 69% energy savings are achieved.