Low-power digital filtering via soft DSP

Rajamohana Hegde, Naresh R. Shanbhag

Research output: Chapter in Book/Report/Conference proceedingConference contribution


We propose a low-power filtering algorithm developed via the soft DSP framework. Soft DSP refers to scaling the supply voltage of a DSP implementation beyond the voltage required to match its critical path delay to the throughput. This deliberate introduction of input-dependent errors leads to degradation in the algorithmic performance, which is then compensated for via algorithmic error-control schemes. The proposed error-control schemes, based on forward/backward linear prediction, provides improved performance over the ones proposed in the past by exploiting correlation in both leading and trailing samples with a latency penalty. It is shown that (a) the proposed scheme provides 60-80% reduction in energy dissipation over that achieved via conventional voltage scaling and (b) for the same algorithmic performance, the overhead involved in the proposed algorithm is more than 50% smaller than existing schemes for medium bandwidth filters.

Original languageEnglish (US)
Title of host publicationDesign and Implementation of Signal Processing SystemNeural Networks for Signal Processing Signal Processing EducationOther Emerging Applications of Signal ProcessingSpecial Sessions
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)0780362934
StatePublished - 2000
Event25th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2000 - Istanbul, Turkey
Duration: Jun 5 2000Jun 9 2000

Publication series

NameICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
ISSN (Print)1520-6149


Other25th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2000

ASJC Scopus subject areas

  • Software
  • Signal Processing
  • Electrical and Electronic Engineering


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