The area and power consumption of oversampling analog-to-digital converters (ADCs) are governed largely by the associated digital decimation filter. This paper presents a low power, area-efficient digital decimation filter for an oversampling ADC application that employs the decorrelating (DECOR) transform in order to reduce the power dissipation and area. The DECOR transform exploits the correlation in the coefficients and data sequences to reduce the precision. Simulation results indicate that a decorrelated 8192-tap decimation filter with a decimation ratio of 64 results in a reduction of 5 bits in the coefficient and accumulator size. This corresponds to savings in complexity of 25%. In multi-stage decimation filters, it is shown that the decimation ratio of the last stage needs to be greater than 4 for DECOR to be useful.
|Original language||English (US)|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - Jan 1 2000|
|Event||Proceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems - Geneva, Switz|
Duration: May 28 2000 → May 31 2000
ASJC Scopus subject areas
- Electrical and Electronic Engineering