Low power and error resilient PN code acquisition filter via statistical error compensation

Eric P. Kim, Daniel J. Baker, Sriram Narayanan, Douglas L Jones, Naresh R. Shanbhag

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present a 256-tap PN code acquisition filter in an 180nm CMOS process employing statistical system-level error compensation. Under voltage overscaling (VOS), near constant detection probability (Pdet) above 90% with 5.8x reduction in energy is achieved at a supply voltage 27% below the point of first failure (PoFF) with an error rate (pe) of 0.868. This is an improvement of 5.8x in energy-efficiency over conventional error free designs and 3.79x in energy-efficiency and 2170x in error tolerance over existing error tolerant designs.

Original languageEnglish (US)
Title of host publication2011 IEEE Custom Integrated Circuits Conference, CICC 2011
DOIs
StatePublished - 2011
Externally publishedYes
Event33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011 - San Jose, CA, United States
Duration: Sep 19 2011Sep 21 2011

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

Other33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011
Country/TerritoryUnited States
CitySan Jose, CA
Period9/19/119/21/11

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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