TY - JOUR
T1 - Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers
AU - Elkholy, Ahmed
AU - Saxena, Saurabh
AU - Shu, Guanghua
AU - Elshazly, Amr
AU - Hanumolu, Pavan Kumar
N1 - Manuscript received November 30, 2017; revised February 11, 2018; accepted March 14, 2018. Date of publication April 16, 2018; date of current version May 24, 2018. This paper was approved by Associate Editor Woogeun Rhee. This work was supported in part by Semiconductor Research Corporation under Grant 1836.124 and in part by Analog Devices. (Corresponding author: Ahmed Elkholy.) A. Elkholy and P. K. Hanumolu are with the Department of Electrical and Computer Engineering, University of Illinois at Urbana–Champaign, Urbana, IL 61801 USA (e-mail: [email protected]). S. Saxena is with the Department of Electrical Engineering, IIT Madras, Chennai 600036, India. G. Shu is with VLSI Research, Oracle Labs, Belmont, CA 94002 USA. A. Elshazly is with Intel Corporation, Hillsboro, OR 97124 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2018.2817602
PY - 2018/6
Y1 - 2018/6
N2 - An all-digital reconfigurable multi-output clock generator is presented. A digital phase-locked loop provides a high-frequency clock to multiple independent open loop ΔΣ fractional dividers (FDIVs). A high resolution digital-to-time converter (DTC) whose range is calibrated in background is used to achieve low-jitter performance that is insensitive to process, voltage, and temperature variations. The proposed open loop FDIV operates over a wide frequency range of 20 MHz-1 GHz, and has programmable spread spectrum modulation and instantaneous frequency switching capabilities. Fabricated in a 65-nm process, the prototype FDIV occupies an active area of 0.017 mm2. At 1-GHz output frequency, it consumes 3.2 mW from 0.9-V supply and achieves a worst case integrated jitter of 1.44 psrms.
AB - An all-digital reconfigurable multi-output clock generator is presented. A digital phase-locked loop provides a high-frequency clock to multiple independent open loop ΔΣ fractional dividers (FDIVs). A high resolution digital-to-time converter (DTC) whose range is calibrated in background is used to achieve low-jitter performance that is insensitive to process, voltage, and temperature variations. The proposed open loop FDIV operates over a wide frequency range of 20 MHz-1 GHz, and has programmable spread spectrum modulation and instantaneous frequency switching capabilities. Fabricated in a 65-nm process, the prototype FDIV occupies an active area of 0.017 mm2. At 1-GHz output frequency, it consumes 3.2 mW from 0.9-V supply and achieves a worst case integrated jitter of 1.44 psrms.
KW - Digitally controlled delay line (DCDL)
KW - delay line
KW - digital phase-locked loop (PLL)
KW - digital-to-time converter (DTC)
KW - dynamic frequency scaling (DFS)
KW - dynamic voltage and frequency scaling (DVFS)
KW - electromagnetic interference (EMI) reduction
KW - fractional divider (FDIV)
KW - fractional-N
KW - frequency switching
KW - frequency synthesizer
KW - spread spectrum clock generator (SSCG)
KW - wide bandwidth (BW)
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U2 - 10.1109/JSSC.2018.2817602
DO - 10.1109/JSSC.2018.2817602
M3 - Article
AN - SCOPUS:85045626945
SN - 0018-9200
VL - 53
SP - 1806
EP - 1817
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 6
ER -