Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers

Ahmed Elkholy; Saurabh Saxena; Guanghua Shu; Amr Elshazly; Pavan Kumar Hanumolu

doi:10.1109/JSSC.2018.2817602

Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers

Ahmed Elkholy, Saurabh Saxena, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu

Research output: Contribution to journal › Article

Abstract

An all-digital reconfigurable multi-output clock generator is presented. A digital phase-locked loop provides a high-frequency clock to multiple independent open loop ΔΣ fractional dividers (FDIVs). A high resolution digital-to-time converter (DTC) whose range is calibrated in background is used to achieve low-jitter performance that is insensitive to process, voltage, and temperature variations. The proposed open loop FDIV operates over a wide frequency range of 20 MHz-1 GHz, and has programmable spread spectrum modulation and instantaneous frequency switching capabilities. Fabricated in a 65-nm process, the prototype FDIV occupies an active area of 0.017 mm². At 1-GHz output frequency, it consumes 3.2 mW from 0.9-V supply and achieves a worst case integrated jitter of 1.44 ps_rms.

Original language	English (US)
Pages (from-to)	1806-1817
Number of pages	12
Journal	IEEE Journal of Solid-State Circuits
Volume	53
Issue number	6
DOIs	https://doi.org/10.1109/JSSC.2018.2817602
State	Published - Jun 2018

Keywords

Digitally controlled delay line (DCDL)
delay line
digital phase-locked loop (PLL)
digital-to-time converter (DTC)
dynamic frequency scaling (DFS)
dynamic voltage and frequency scaling (DVFS)
electromagnetic interference (EMI) reduction
fractional divider (FDIV)
fractional-N
frequency switching
frequency synthesizer
spread spectrum clock generator (SSCG)
wide bandwidth (BW)

ASJC Scopus subject areas

Electrical and Electronic Engineering

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Elkholy, A., Saxena, S., Shu, G., Elshazly, A., & Hanumolu, P. K. (2018). Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers. IEEE Journal of Solid-State Circuits, 53(6), 1806-1817. https://doi.org/10.1109/JSSC.2018.2817602

@article{ac7ae9b99d8f4df8aa7495f16970e3cf,

title = "Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers",

abstract = "An all-digital reconfigurable multi-output clock generator is presented. A digital phase-locked loop provides a high-frequency clock to multiple independent open loop ΔΣ fractional dividers (FDIVs). A high resolution digital-to-time converter (DTC) whose range is calibrated in background is used to achieve low-jitter performance that is insensitive to process, voltage, and temperature variations. The proposed open loop FDIV operates over a wide frequency range of 20 MHz-1 GHz, and has programmable spread spectrum modulation and instantaneous frequency switching capabilities. Fabricated in a 65-nm process, the prototype FDIV occupies an active area of 0.017 mm2. At 1-GHz output frequency, it consumes 3.2 mW from 0.9-V supply and achieves a worst case integrated jitter of 1.44 psrms.",

keywords = "Digitally controlled delay line (DCDL), delay line, digital phase-locked loop (PLL), digital-to-time converter (DTC), dynamic frequency scaling (DFS), dynamic voltage and frequency scaling (DVFS), electromagnetic interference (EMI) reduction, fractional divider (FDIV), fractional-N, frequency switching, frequency synthesizer, spread spectrum clock generator (SSCG), wide bandwidth (BW)",

author = "Ahmed Elkholy and Saurabh Saxena and Guanghua Shu and Amr Elshazly and Hanumolu, {Pavan Kumar}",

year = "2018",

month = jun,

doi = "10.1109/JSSC.2018.2817602",

language = "English (US)",

volume = "53",

pages = "1806--1817",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "6",

}

TY - JOUR

T1 - Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers

AU - Elkholy, Ahmed

AU - Saxena, Saurabh

AU - Shu, Guanghua

AU - Elshazly, Amr

AU - Hanumolu, Pavan Kumar

PY - 2018/6

Y1 - 2018/6

N2 - An all-digital reconfigurable multi-output clock generator is presented. A digital phase-locked loop provides a high-frequency clock to multiple independent open loop ΔΣ fractional dividers (FDIVs). A high resolution digital-to-time converter (DTC) whose range is calibrated in background is used to achieve low-jitter performance that is insensitive to process, voltage, and temperature variations. The proposed open loop FDIV operates over a wide frequency range of 20 MHz-1 GHz, and has programmable spread spectrum modulation and instantaneous frequency switching capabilities. Fabricated in a 65-nm process, the prototype FDIV occupies an active area of 0.017 mm2. At 1-GHz output frequency, it consumes 3.2 mW from 0.9-V supply and achieves a worst case integrated jitter of 1.44 psrms.

AB - An all-digital reconfigurable multi-output clock generator is presented. A digital phase-locked loop provides a high-frequency clock to multiple independent open loop ΔΣ fractional dividers (FDIVs). A high resolution digital-to-time converter (DTC) whose range is calibrated in background is used to achieve low-jitter performance that is insensitive to process, voltage, and temperature variations. The proposed open loop FDIV operates over a wide frequency range of 20 MHz-1 GHz, and has programmable spread spectrum modulation and instantaneous frequency switching capabilities. Fabricated in a 65-nm process, the prototype FDIV occupies an active area of 0.017 mm2. At 1-GHz output frequency, it consumes 3.2 mW from 0.9-V supply and achieves a worst case integrated jitter of 1.44 psrms.

KW - Digitally controlled delay line (DCDL)

KW - delay line

KW - digital phase-locked loop (PLL)

KW - digital-to-time converter (DTC)

KW - dynamic frequency scaling (DFS)

KW - dynamic voltage and frequency scaling (DVFS)

KW - electromagnetic interference (EMI) reduction

KW - fractional divider (FDIV)

KW - fractional-N

KW - frequency switching

KW - frequency synthesizer

KW - spread spectrum clock generator (SSCG)

KW - wide bandwidth (BW)

UR - http://www.scopus.com/inward/record.url?scp=85045626945&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85045626945&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2018.2817602

DO - 10.1109/JSSC.2018.2817602

M3 - Article

AN - SCOPUS:85045626945

VL - 53

SP - 1806

EP - 1817

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 6

ER -