Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers

Ahmed Elkholy, Saurabh Saxena, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu

Research output: Contribution to journalArticle

Abstract

An all-digital reconfigurable multi-output clock generator is presented. A digital phase-locked loop provides a high-frequency clock to multiple independent open loop ΔΣ fractional dividers (FDIVs). A high resolution digital-to-time converter (DTC) whose range is calibrated in background is used to achieve low-jitter performance that is insensitive to process, voltage, and temperature variations. The proposed open loop FDIV operates over a wide frequency range of 20 MHz-1 GHz, and has programmable spread spectrum modulation and instantaneous frequency switching capabilities. Fabricated in a 65-nm process, the prototype FDIV occupies an active area of 0.017 mm2. At 1-GHz output frequency, it consumes 3.2 mW from 0.9-V supply and achieves a worst case integrated jitter of 1.44 psrms.

Original languageEnglish (US)
Pages (from-to)1806-1817
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Volume53
Issue number6
DOIs
StatePublished - Jun 2018

Keywords

  • Digitally controlled delay line (DCDL)
  • delay line
  • digital phase-locked loop (PLL)
  • digital-to-time converter (DTC)
  • dynamic frequency scaling (DFS)
  • dynamic voltage and frequency scaling (DVFS)
  • electromagnetic interference (EMI) reduction
  • fractional divider (FDIV)
  • fractional-N
  • frequency switching
  • frequency synthesizer
  • spread spectrum clock generator (SSCG)
  • wide bandwidth (BW)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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