The authors examine the mapping of logic simulation onto massively parallel computer architectures. They discuss alternative communication primitives for a massively parallel instruction set architecture and the impact of the choice of communication primitives on logic simulation. They have developed compilation tools to map the simulation of an MOS transistor circuit onto a massively parallel computer automatically. The authors also analyze the efficiency of this mapping as a function of the available communication primitives. The compilation process is illustrated by describing a pilot implementation on a 32K processor Connection Machine.
|Original language||English (US)|
|Number of pages||8|
|Journal||Conference Proceedings - Annual Symposium on Computer Architecture|
|State||Published - 1989|
|Event||16th Annual International Symposium on Computer Architecture - Jerusalem, Israel|
Duration: May 28 1989 → Jun 1 1989
ASJC Scopus subject areas