Logic simulation on massively parallel architectures.

Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar

Research output: Contribution to journalConference articlepeer-review

Abstract

The authors examine the mapping of logic simulation onto massively parallel computer architectures. They discuss alternative communication primitives for a massively parallel instruction set architecture and the impact of the choice of communication primitives on logic simulation. They have developed compilation tools to map the simulation of an MOS transistor circuit onto a massively parallel computer automatically. The authors also analyze the efficiency of this mapping as a function of the available communication primitives. The compilation process is illustrated by describing a pilot implementation on a 32K processor Connection Machine.

Original languageEnglish (US)
Pages (from-to)336-343
Number of pages8
JournalConference Proceedings - Annual Symposium on Computer Architecture
Issue number16
DOIs
StatePublished - 1989
Event16th Annual International Symposium on Computer Architecture - Jerusalem, Israel
Duration: May 28 1989Jun 1 1989

ASJC Scopus subject areas

  • Engineering(all)

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