Lithography-aware layout modification considering performance impact

Hongbo Zhang, Yuelin Du, Martin D.F. Wong, Kai Yuan Chao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As regular design rules become necessary in sub-45nm node circuit design, 1-D design has shown its advantages and has drawn intensive research interest. In 1-D design, line-end gaps are the main sources of printing difficulties. Recently, we [5] demonstrated that printability can be significantly improved by intelligent (litho-aware) rearrangement of the gap distribution with techniques such as line-end extension and dummy insertion. Note that poly/gate redistribution techniques require layout modification of the original layout and thus will impact circuit performance and power consumption. Such potentially undesirable impacts on performance and power were not considered in [5] and deserve a careful investigation, which is the subject of our study. In this paper, we present performance-driven gate redistribution algorithms which consider bounds on line-end extension. Experimental results demonstrate the feasibility of our algorithms, and lithography simulation and circuit analysis show the trend of the trade off between printability, delay, and power.

Original languageEnglish (US)
Title of host publicationProceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011
Pages437-441
Number of pages5
DOIs
StatePublished - Jun 22 2011
Event12th International Symposium on Quality Electronic Design, ISQED 2011 - Santa Clara, CA, United States
Duration: Mar 14 2011Mar 16 2011

Publication series

NameProceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011

Other

Other12th International Symposium on Quality Electronic Design, ISQED 2011
CountryUnited States
CitySanta Clara, CA
Period3/14/113/16/11

    Fingerprint

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Zhang, H., Du, Y., Wong, M. D. F., & Chao, K. Y. (2011). Lithography-aware layout modification considering performance impact. In Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011 (pp. 437-441). [5770763] (Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011). https://doi.org/10.1109/ISQED.2011.5770763