Limitations of VLSI implementation of delay-sensitive codes

Venkatesh Akella, Nitin H. Vaidya, G. Robert Redinbo

Research output: Contribution to journalConference articlepeer-review

Abstract

Implementation of delay-insensitive (DI) or unordered codes is the subject of this paper. We present two different architectures for decoding systematic DI codes: (a) enumeration-based decoder, and (b) comparison-based decoder. We argue that enumeration-based decoders are often impractical for many realistic codes. Comparison-based decoders that detect arrival of a code word by comparing the received checkbits with checkbits evaluated using the received data are practical but suffer from the following limitation. If the decoder is to be implemented using asynchronous logic, i.e., if the gate and wire delays are arbitrary (unbounded but finite), then it is impossible to design a comparison-based decoder for any code that is more efficient than a dual-rail code. In other words, the encoded word must contain at least twice as many bits as the data. The paper shows that comparison-based decoders for codes that have the requisite level of redundancy can be implemented using asynchronous logic. The paper also shows that, by relaxing the delay assumptions, it is possible to implement decoders for delay-insensitive codes that are more efficient than dual-rail codes.

Original languageEnglish (US)
Pages (from-to)208-217
Number of pages10
JournalProceedings - Annual International Conference on Fault-Tolerant Computing
StatePublished - 1996
Externally publishedYes
EventProceedings of the 1996 26th International Symposium on Fault-Tolerant Computing - Sendai, Jpn
Duration: Jun 25 1996Jun 27 1996

ASJC Scopus subject areas

  • Hardware and Architecture

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