LIM Algorithms for Diodes and Branch Capacitors

Jose Schutt-Aine, Patrick Goh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The latency insertion method (LIM) has been demonstrated as an optimum algorithm for the transient simulation of large networks. However, several network topologies and circuit elements do not lead to a LIM-compatible formulation. This work addresses the derivation of LIM expressions for non-standard topologies and elements. In particular, we address the formulation for nonlinear elements and branch capacitors. Examples and comparisons are given for evaluating the algorithms.

Original languageEnglish (US)
Title of host publicationIEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538665923
DOIs
StatePublished - Jul 2 2018
Event2018 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2018 - Chandigarh, India
Duration: Dec 16 2018Dec 18 2018

Publication series

NameIEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2018

Conference

Conference2018 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2018
CountryIndia
CityChandigarh
Period12/16/1812/18/18

    Fingerprint

Keywords

  • latency
  • simulation
  • time step
  • transient

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Schutt-Aine, J., & Goh, P. (2018). LIM Algorithms for Diodes and Branch Capacitors. In IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2018 [8680874] (IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDAPS.2018.8680874