TY - GEN
T1 - Lightning Talk
T2 - 60th ACM/IEEE Design Automation Conference, DAC 2023
AU - Chen, Deming
N1 - We have surveyed the recent advances in HLS and highlighted the challenges and opportunities that will shape the next wave of HLS research. The related research areas, including language, compiler, EDA, AI, and circuits, need to collaborate in order to take advantage of the new opportunities and benefit the entire semiconductor industry. Our HLS research has been supported by NSF 2117997 grant through the A3D3 center, SRC 2023-CT-3175 grant, AMD Center of Excellence, and the BAH HT 15-1158 grant. The author would like to thank Hanchen Ye of UIUC for providing raw materials for this article.
PY - 2023
Y1 - 2023
N2 - Recent works established new High-Level Synthesis (HLS) solutions translating AI models described in PyTorch to customized AI accelerators automatically. By adopting PyTorch as input for AI designs (instead of traditional C/C++ for HLS), the lines of code and design simulation time can be reduced by about 10× and 100×, respectively. Such AI model-to-RTL flows pave the way for a new wave of HLS that could drive the high-productivity designs of AI circuits with high-density, high-energy efficiency, low cost, and short design cycle. And such high-level model-to-RTL flows can be expanded to other non-AI domains. Meanwhile, we are also facing existing and new challenges for such HLS solutions, such as ensuring the correctness of the high-level design, accommodating accurate low-level timing/energy information, handling the complexity of 3D circuits and/or chiplet-based design flows, and achieving all these in a highly scalable manner. In this paper, we share the state-of-the-art solutions, limitations, and new opportunities facing the emergence of a new wave of the next-generation HLS.
AB - Recent works established new High-Level Synthesis (HLS) solutions translating AI models described in PyTorch to customized AI accelerators automatically. By adopting PyTorch as input for AI designs (instead of traditional C/C++ for HLS), the lines of code and design simulation time can be reduced by about 10× and 100×, respectively. Such AI model-to-RTL flows pave the way for a new wave of HLS that could drive the high-productivity designs of AI circuits with high-density, high-energy efficiency, low cost, and short design cycle. And such high-level model-to-RTL flows can be expanded to other non-AI domains. Meanwhile, we are also facing existing and new challenges for such HLS solutions, such as ensuring the correctness of the high-level design, accommodating accurate low-level timing/energy information, handling the complexity of 3D circuits and/or chiplet-based design flows, and achieving all these in a highly scalable manner. In this paper, we share the state-of-the-art solutions, limitations, and new opportunities facing the emergence of a new wave of the next-generation HLS.
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U2 - 10.1109/DAC56929.2023.10247880
DO - 10.1109/DAC56929.2023.10247880
M3 - Conference contribution
AN - SCOPUS:85173097910
T3 - Proceedings - Design Automation Conference
BT - 2023 60th ACM/IEEE Design Automation Conference, DAC 2023
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 9 July 2023 through 13 July 2023
ER -