TY - GEN
T1 - Leveraging dynamic partial reconfiguration with scalable ILP based task scheduling
AU - Dhar, Ashutosh
AU - Yu, Mang
AU - Zuo, Wei
AU - Wang, Xiaohao
AU - Kim, Nam Sung
AU - Chen, Deming
N1 - Funding Information:
VI. CONCLUSION In this work we demonstrated the effectiveness of using dynamic partial reconfiguration for mapping computational workloads. We presented an end-to-end and universal solution that considers FPGAs of all sizes, and is capable of simultaneous mapping of multiple applications and parallel pipelines to the same FPGA. Our solution includes an architecture that limits design effort for scalability and portability, a methodology to map workloads, and an ILP based scheduler to provide the lowestlatency schedule. Our proposed methodology is generic, and not restricted to a particular domain. We demonstrated the efficacy, high resource efficiency, and performance of our approach. Our ILP-based scheduler’s ability to pipeline and parallelize provided up to 3.9X in performance gains. Finally, we presented a partitioning solution to map large graphs and multiple applications, and demonstrated the scheduling and mapping of 11 applications simultaneously to a single FPGA. ACKNOWLEDGMENT This work is supported by IBM-ILLINOIS Center for Cognitive Computing Systems Research (C3SR) - a research collaboration as part of the IBM AI Horizons Network. REFERENCES
Publisher Copyright:
© 2020 IEEE.
PY - 2020/1
Y1 - 2020/1
N2 - FPGA-based computation has shown better latency and energy efficiency compared to CPU or GPU-based solutions. However, as the complexity of emerging applications has significantly grown, it is difficult to efficiently utilize the FPGA. Thus, there is a renewed interest to deploy dynamic partial reconfiguration for FPGA-based hardware from both the industry and the academic community. In this work we demonstrate a methodology for scheduling heterogenous tasks across given FPGA resources in a resource efficient manner while effectively hiding latency of dynamic partial reconfiguration. With the help of an ILP based scheduler, we demonstrate the mapping of diverse computational workloads in both cloud and edge-like scenarios. Our novel contribution includes enabling pipelining and parallelization of batches in our scheduler. Our scheduler is capable of masking reconfiguration overheads, and its ability to pipeline across batches demonstrated up to 3.9X improvements. Finally, our scalable scheduler is capable of simultaneously mapping 11 applications to a single cloud-scale, as well as edge-scale, FPGA.
AB - FPGA-based computation has shown better latency and energy efficiency compared to CPU or GPU-based solutions. However, as the complexity of emerging applications has significantly grown, it is difficult to efficiently utilize the FPGA. Thus, there is a renewed interest to deploy dynamic partial reconfiguration for FPGA-based hardware from both the industry and the academic community. In this work we demonstrate a methodology for scheduling heterogenous tasks across given FPGA resources in a resource efficient manner while effectively hiding latency of dynamic partial reconfiguration. With the help of an ILP based scheduler, we demonstrate the mapping of diverse computational workloads in both cloud and edge-like scenarios. Our novel contribution includes enabling pipelining and parallelization of batches in our scheduler. Our scheduler is capable of masking reconfiguration overheads, and its ability to pipeline across batches demonstrated up to 3.9X improvements. Finally, our scalable scheduler is capable of simultaneously mapping 11 applications to a single cloud-scale, as well as edge-scale, FPGA.
KW - ILP
KW - Partial Reconfiguration
KW - Scheduling
UR - http://www.scopus.com/inward/record.url?scp=85089184153&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85089184153&partnerID=8YFLogxK
U2 - 10.1109/VLSID49098.2020.00052
DO - 10.1109/VLSID49098.2020.00052
M3 - Conference contribution
AN - SCOPUS:85089184153
T3 - Proceedings - 33rd International Conference on VLSI Design, VLSID 2020 - Held concurrently with 19th International Conference on Embedded Systems
SP - 201
EP - 206
BT - Proceedings - 33rd International Conference on VLSI Design, VLSID 2020 - Held concurrently with 19th International Conference on Embedded Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 33rd International Conference on VLSI Design, VLSID 2020
Y2 - 4 January 2020 through 8 January 2020
ER -