LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory

Amirali Boroumand, Saugata Ghose, Minesh Patel, Hasan Hassan, Brandon Lucia, Kevin Hsieh, Krishna T. Malladi, Hongzhong Zheng, Onur Mutlu

Research output: Contribution to journalArticlepeer-review

Abstract

Processing-in-memory (PIM) architectures cannot use traditional approaches to cache coherence due to the high off-chip traffic consumed by coherence messages. We propose LazyPIM, a new hardware cache coherence mechanism designed specifically for PIM. LazyPIM uses a combination of speculative cache coherence and compressed coherence signatures to greatly reduce the overhead of keeping PIM coherent with the processor. We find that LazyPIM improves average performance across a range of PIM applications by 49.1 percent over the best prior approach, coming within 5.5 percent of an ideal PIM mechanism.

Original languageEnglish (US)
Article number7485993
Pages (from-to)46-50
Number of pages5
JournalIEEE Computer Architecture Letters
Volume16
Issue number1
DOIs
StatePublished - Jan 1 2017
Externally publishedYes

ASJC Scopus subject areas

  • Hardware and Architecture

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