Abstract
Processing-in-memory (PIM) architectures cannot use traditional approaches to cache coherence due to the high off-chip traffic consumed by coherence messages. We propose LazyPIM, a new hardware cache coherence mechanism designed specifically for PIM. LazyPIM uses a combination of speculative cache coherence and compressed coherence signatures to greatly reduce the overhead of keeping PIM coherent with the processor. We find that LazyPIM improves average performance across a range of PIM applications by 49.1 percent over the best prior approach, coming within 5.5 percent of an ideal PIM mechanism.
Original language | English (US) |
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Article number | 7485993 |
Pages (from-to) | 46-50 |
Number of pages | 5 |
Journal | IEEE Computer Architecture Letters |
Volume | 16 |
Issue number | 1 |
DOIs | |
State | Published - Jan 1 2017 |
Externally published | Yes |
ASJC Scopus subject areas
- Hardware and Architecture