Abstract
Layout options for CMOS ESD diodes' p-n junction geometry and metal routing are investigated in this paper. Experiments are performed using 90- and 180-nm technologies. Using the figures of merit $I-{\rm CP}/C$ and $R-{\rm ON} \ast C$, it is shown that twin-well stripe diodes with nonminimum diffusion width and high-level broadside routing are optimum for gigahertz-frequency I/Os. In addition, the suitability of ESD diodes formed with the isolated P-well/deep N-well diffusions available in triple-well technologies is evaluated for high-speed I/O applications.
Original language | English (US) |
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Article number | 5153318 |
Pages (from-to) | 465-475 |
Number of pages | 11 |
Journal | IEEE Transactions on Device and Materials Reliability |
Volume | 9 |
Issue number | 3 |
DOIs | |
State | Published - Sep 2009 |
Keywords
- CMOS integrated circuits
- Diodes
- Electrostatic discharges
- Metallization
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Safety, Risk, Reliability and Quality
- Electrical and Electronic Engineering