Layout guidelines for optimized ESD protection diodes

Karan Bhatia, Elyse Rosenbaum

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this work, various layout options for ESD diodes' PN junction geometry and metal routing are investigated. The current compression point (I CP) is introduced to define the maximum current handling capability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the performance of the structures investigated herein.

Original languageEnglish (US)
Title of host publication2007 29th Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD
DOIs
StatePublished - Dec 1 2007
Event2007 29th Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD - Anaheim, CA, United States
Duration: Sep 16 2007Sep 21 2007

Publication series

NameElectrical Overstress/Electrostatic Discharge Symposium Proceedings
ISSN (Print)0739-5159

Other

Other2007 29th Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD
CountryUnited States
CityAnaheim, CA
Period9/16/079/21/07

ASJC Scopus subject areas

  • Condensed Matter Physics

Fingerprint Dive into the research topics of 'Layout guidelines for optimized ESD protection diodes'. Together they form a unique fingerprint.

Cite this