Layer-by-layer assembly of nanowires for three-dimensional, multifunctional electronics

Ali Javey, Sung Woo Nam, Robin S. Friedman, Hao Yan, Charles M. Lieber

Research output: Contribution to journalArticle

Abstract

We report a general approach for three-dimensional (3D) multifunctional electronics based on the layer-by-layer assembly of nanowire (NW) building blocks. Using germanium/silicon (Ge/Si) core/shell NWs as a representative example, ten vertically stacked layers of multi-NW field-effect transistors (FETs) were fabricated. Transport measurements demonstrate that the Ge/Si NW FETs have reproducible high-performance device characteristics within a given device layer, that the FET characteristics are not affected by sequential stacking, and importantly, that uniform performance is achieved in sequential layers 1 through 10 of the 3D structure. Five-layer single-NW FET structures were also prepared by printing Ge/Si NWs from lower density growth substrates, and transport measurements showed similar high-performance characteristics for the FETs in layers 1 and 5. In addition, 3D multifunctional circuitry was demonstrated on plastic substrates with sequential layers of inverter logical gates and floating gate memory elements. Notably, electrical characterization studies show stable writing and erasing of the NW floating gate memory elements and demonstrate signal inversion with larger than unity gain for frequencies up to at least 50 MHz. The ability to assemble reproducibly sequential layers of distinct types of NW-based devices coupled with the breadth of NW building blocks should enable the assembly of increasing complex multilayer and multifunctional 3D electronics in the future.

Original languageEnglish (US)
Pages (from-to)773-777
Number of pages5
JournalNano letters
Volume7
Issue number3
DOIs
StatePublished - Mar 2007
Externally publishedYes

ASJC Scopus subject areas

  • Bioengineering
  • Chemistry(all)
  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanical Engineering

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