LATTICE-MESH: A MULTI-BUS ARCHITECTURE.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A new multibus topology called the lattice-mesh is proposed. It is compared with other multibus architectures on the basis of established criteria such as the internode distance and of a new criterion called the hits variance. This criterion is relevant for a subclass of parallel systems that execute tree-structured computations. These systems require that the parent and child nodes of the computation tree be mapped onto adjacent processors. The lattice-mesh is seen to have very good scalability.

Original languageEnglish (US)
Title of host publicationProceedings of the International Conference on Parallel Processing
EditorsDouglas DeGroot
PublisherIEEE
Pages700-702
Number of pages3
ISBN (Print)0818606371
StatePublished - 1985
Externally publishedYes

ASJC Scopus subject areas

  • Hardware and Architecture

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