@inproceedings{66c5b5db421c443bb06fead5f544b67b,
title = "Latency insertion method with variable time step",
abstract = "This paper presents a variation of the Latency Insertion Method (LIM) with variable time step. LIM is an alternative to SPICE that is capable of performing fast transient simulations to large systems. This version uses the voltage-in-current formulation to allow bigger time steps than basic LIM, then uses local truncation error (LTE) as the criteria to vary the time step during simulation while maintaining accuracy. Examples including accuracy and run time comparisons are provided.",
keywords = "latency, simulation, time step, transient",
author = "Gene Shiue and Schutt-Aine, {Jose E.} and Patrick Goh",
note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2019 ; Conference date: 16-12-2019 Through 18-12-2019",
year = "2019",
month = dec,
doi = "10.1109/EDAPS47854.2019.9011649",
language = "English (US)",
series = "IEEE Electrical Design of Advanced Packaging and Systems Symposium",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "EDAPS 2019 - Electrical Design of Advanced Packaging and Systems Symposium",
address = "United States",
}