Latency insertion method (LIM) for DC analysis of power supply networks

Process scaling in modern integrated circuits has led to multiple signal and power integrity issues. In particular, ensuring reliable performance of on-chip power delivery systems has become a major design challenge. Rigorous analysis and simulations are required at the design stage to ensure proper functionality of an on-chip power supply. This puts a strain on existing numerical tools due to the sheer size of the power grids. In this paper, a fast circuit simulation technique based on the latency insertion method (LIM) is proposed for the steady-state analysis of large-scale circuits, such as on-chip power distribution network. The proposed method is shown to be very efficient for modeling of networks with very large numbers of nodes. The comparison with one of the well-established methods used for the power grid analysis today, the Random-Walk algorithm, shows that LIM is almost two orders of magnitude faster.