Latency insertion method (LIM) for DC analysis of power supply networks

Dmitri Klokotov, Patrick Goh, José E. Schutt-Ainé

Research output: Contribution to journalArticlepeer-review


Process scaling in modern integrated circuits has led to multiple signal and power integrity issues. In particular, ensuring reliable performance of on-chip power delivery systems has become a major design challenge. Rigorous analysis and simulations are required at the design stage to ensure proper functionality of an on-chip power supply. This puts a strain on existing numerical tools due to the sheer size of the power grids. In this paper, a fast circuit simulation technique based on the latency insertion method (LIM) is proposed for the steady-state analysis of large-scale circuits, such as on-chip power distribution network. The proposed method is shown to be very efficient for modeling of networks with very large numbers of nodes. The comparison with one of the well-established methods used for the power grid analysis today, the Random-Walk algorithm, shows that LIM is almost two orders of magnitude faster.

Original languageEnglish (US)
Article number6009178
Pages (from-to)1839-1845
Number of pages7
JournalIEEE Transactions on Components, Packaging and Manufacturing Technology
Issue number11
StatePublished - Nov 2011


  • DC analysis
  • IR-drop
  • latency insertion
  • latency insertion method
  • power distribution network
  • power integrity
  • power supply

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering


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