Latency Insertion Method (LIM) for CMOS circuit simulations with multi-rate considerations

Patrick Goh; José E. Schutt-Ainé

doi:10.1109/EPEPS.2011.6100205

Latency Insertion Method (LIM) for CMOS circuit simulations with multi-rate considerations

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, we present an application of the latency insertion method (LIM) to the transient simulations of CMOS circuits and compare it to traditional SPICE based methods. In addition, we extend the multi-rate simulation technique and apply it to the simulation of CMOS circuits in the LIM environment and illustrate its computational efficiently over the basic LIM.

Original language	English (US)
Title of host publication	2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011
Pages	125-128
Number of pages	4
DOIs	https://doi.org/10.1109/EPEPS.2011.6100205
State	Published - 2011
Event	2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011 - San Jose, CA, United States Duration: Oct 23 2011 → Oct 26 2011

Publication series

Name	2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011

Other

Other	2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011
Country/Territory	United States
City	San Jose, CA
Period	10/23/11 → 10/26/11

Keywords

CMOS
circuit simulation
latency insertion method (LIM)
multi-rate simulation

ASJC Scopus subject areas

Electrical and Electronic Engineering

Online availability

10.1109/EPEPS.2011.6100205

Library availability

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Goh, P., & Schutt-Ainé, J. E. (2011). Latency Insertion Method (LIM) for CMOS circuit simulations with multi-rate considerations. In 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011 (pp. 125-128). Article 6100205 (2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011). https://doi.org/10.1109/EPEPS.2011.6100205

Latency Insertion Method (LIM) for CMOS circuit simulations with multi-rate considerations. / Goh, Patrick; Schutt-Ainé, José E.
2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011. 2011. p. 125-128 6100205 (2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Goh, P & Schutt-Ainé, JE 2011, Latency Insertion Method (LIM) for CMOS circuit simulations with multi-rate considerations. in 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011., 6100205, 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011, pp. 125-128, 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011, San Jose, CA, United States, 10/23/11. https://doi.org/10.1109/EPEPS.2011.6100205

Goh P, Schutt-Ainé JE. Latency Insertion Method (LIM) for CMOS circuit simulations with multi-rate considerations. In 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011. 2011. p. 125-128. 6100205. (2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011). doi: 10.1109/EPEPS.2011.6100205

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Latency Insertion Method (LIM) for CMOS circuit simulations with multi-rate considerations

Abstract

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Keywords

ASJC Scopus subject areas

Online availability

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