@inproceedings{4741c96087414461b5b1221e857e8932,
title = "Latency Insertion Method for FinFET Simulation Incorporating Parasitic Source/Drain Resistances",
abstract = "Three-dimensional FinFETs with well-suppressed short channel effects and low power consumption were introduced to replace traditional planar MOSFETs in sub-20 nm devices. However, the three-dimensional structure introduces numerous complex parasitic effects, which makes the simulation challenging. Developing fast and accurate simulation algorithms for FinFETs is thus critical to reduce verification time. The Latency Insertion Method (LIM) proved to be able to provide accurate and fast FinFET DC simulation in our previous work. In this paper, we focus on improving the robustness of the algorithm by incorporating parasitic source/drain resistances. Following the BSIM-CMG compact model, we introduced the LIM schematics for three different parasitic resistance modes. The simulation results of LIM are compared with commercial simulators to verify the accuracy and speed.",
keywords = "BSIM-CMG, circuit simulation, compact model, FinFET, latency insertion method",
author = "Yi Zhou and Schutt-Ain{\'e}, {Jos{\'e} E.}",
note = "This material is based upon work supported by the U.S Army Small Business Innovation Research (SBIR) Program office and the U.S. Army Research Office under Contract No. W911NF-15-P-0005.; 10th IEEE Electronics System-Integration Technology Conference, ESTC 2024 ; Conference date: 11-09-2024 Through 13-09-2024",
year = "2024",
doi = "10.1109/ESTC60143.2024.10712107",
language = "English (US)",
series = "2024 IEEE 10th Electronics System-Integration Technology Conference, ESTC 2024 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2024 IEEE 10th Electronics System-Integration Technology Conference, ESTC 2024 - Proceedings",
address = "United States",
}