@inproceedings{5d7ce152b5714c1a9f2c97d5db49e97e,
title = "Latency Insertion Method for FinFET DC Operating Point Simulation Based on BSIM-CMG",
abstract = "As the scaling of planar MOSFETs progresses, various short-channel effects become prominent. The 3-dimensional FinFET was invented to avoid these short-channel effects. Transistor-level simulation with FinFETs is traditionally conducted by SPICE which has super-linear computational complexity. We propose a new method for FinFET DC operating point simulation through the use of the latency insertion method (LIM) which exhibits linear computational complexity. The algorithm incorporates the BSIM-CMG industry-standard compact model. The method is tested on 10 nm and 20 nm FinFETs, and the results are compared with commercial simulators.",
keywords = "BSIM-CMG, FinFET, circuit simulation, compact model, integrated circuit, latency insertion method",
author = "Yi Zhou and Schutt-Aine, {Jose E.}",
note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 IEEE Electrical Design of Advanced Packaging and Systems, EDAPS 2022 ; Conference date: 12-12-2022 Through 14-12-2022",
year = "2022",
doi = "10.1109/EDAPS56906.2022.9995055",
language = "English (US)",
series = "IEEE Electrical Design of Advanced Packaging and Systems Symposium",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2022 IEEE Electrical Design of Advanced Packaging and Systems, EDAPS 2022",
address = "United States",
}