Latency Insertion Method for FinFET DC Operating Point Simulation Based on BSIM-CMG

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As the scaling of planar MOSFETs progresses, various short-channel effects become prominent. The 3-dimensional FinFET was invented to avoid these short-channel effects. Transistor-level simulation with FinFETs is traditionally conducted by SPICE which has super-linear computational complexity. We propose a new method for FinFET DC operating point simulation through the use of the latency insertion method (LIM) which exhibits linear computational complexity. The algorithm incorporates the BSIM-CMG industry-standard compact model. The method is tested on 10 nm and 20 nm FinFETs, and the results are compared with commercial simulators.

Original languageEnglish (US)
Title of host publication2022 IEEE Electrical Design of Advanced Packaging and Systems, EDAPS 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665491945
DOIs
StatePublished - 2022
Event2022 IEEE Electrical Design of Advanced Packaging and Systems, EDAPS 2022 - Urbana, United States
Duration: Dec 12 2022Dec 14 2022

Publication series

NameIEEE Electrical Design of Advanced Packaging and Systems Symposium
Volume2022-December
ISSN (Print)2151-1225
ISSN (Electronic)2151-1233

Conference

Conference2022 IEEE Electrical Design of Advanced Packaging and Systems, EDAPS 2022
Country/TerritoryUnited States
CityUrbana
Period12/12/2212/14/22

Keywords

  • BSIM-CMG
  • circuit simulation
  • compact model
  • FinFET
  • integrated circuit
  • latency insertion method

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Automotive Engineering
  • General Computer Science

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