Latency-Aware Generation of Single-Rate DAGs from Multi-Rate Task Sets

Micaela Verucchi; Mirco Theile; Marco Caccamo; Marko Bertogna

doi:10.1109/RTAS48715.2020.000-4

Latency-Aware Generation of Single-Rate DAGs from Multi-Rate Task Sets

Micaela Verucchi, Mirco Theile, Marco Caccamo, Marko Bertogna

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Modern automotive and avionics embedded systems integrate several functionalities that are subject to complex timing requirements. A typical application in these fields is composed of sensing, computation, and actuation. The ever increasing complexity of heterogeneous sensors implies the adoption of multi-rate task models scheduled onto parallel platforms. Aspects like freshness of data or first reaction to an event are crucial for the performance of the system. The Directed Acyclic Graph (DAG) is a suitable model to express the complexity and the parallelism of these tasks. However, deriving age and reaction timing bounds is not trivial when DAG tasks have multiple rates. In this paper, a method is proposed to convert a multi-rate DAG task-set with timing constraints into a single-rate DAG that optimizes schedulability, age and reaction latency, by inserting suitable synchronization constructs. An experimental evaluation is presented for an autonomous driving benchmark, validating the proposed approach against state-of-the-art solutions.

Original language	English (US)
Title of host publication	Proceedings - 2020 IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	226-238
Number of pages	13
ISBN (Electronic)	9781728154992
DOIs	https://doi.org/10.1109/RTAS48715.2020.000-4
State	Published - Apr 2020
Externally published	Yes
Event	26th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2020 - Sydney, Australia Duration: Apr 21 2020 → Apr 24 2020

Publication series

Name	Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS
Volume	2020-April
ISSN (Print)	1545-3421

Conference

Conference	26th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2020
Country	Australia
City	Sydney
Period	4/21/20 → 4/24/20

Keywords

DAG
end-to-end latency
multi-rate
schedulability

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1109/RTAS48715.2020.000-4

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Cite this

Verucchi, M., Theile, M., Caccamo, M., & Bertogna, M. (2020). Latency-Aware Generation of Single-Rate DAGs from Multi-Rate Task Sets. In Proceedings - 2020 IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2020 (pp. 226-238). [9113118] (Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS; Vol. 2020-April). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RTAS48715.2020.000-4

Latency-Aware Generation of Single-Rate DAGs from Multi-Rate Task Sets. / Verucchi, Micaela; Theile, Mirco; Caccamo, Marco; Bertogna, Marko.

Proceedings - 2020 IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 226-238 9113118 (Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS; Vol. 2020-April).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Verucchi, M, Theile, M, Caccamo, M & Bertogna, M 2020, Latency-Aware Generation of Single-Rate DAGs from Multi-Rate Task Sets. in Proceedings - 2020 IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2020., 9113118, Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS, vol. 2020-April, Institute of Electrical and Electronics Engineers Inc., pp. 226-238, 26th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2020, Sydney, Australia, 4/21/20. https://doi.org/10.1109/RTAS48715.2020.000-4

Verucchi M, Theile M, Caccamo M, Bertogna M. Latency-Aware Generation of Single-Rate DAGs from Multi-Rate Task Sets. In Proceedings - 2020 IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 226-238. 9113118. (Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS). https://doi.org/10.1109/RTAS48715.2020.000-4

Verucchi, Micaela ; Theile, Mirco ; Caccamo, Marco ; Bertogna, Marko. / Latency-Aware Generation of Single-Rate DAGs from Multi-Rate Task Sets. Proceedings - 2020 IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2020. Institute of Electrical and Electronics Engineers Inc., 2020. pp. 226-238 (Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS).

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