Latch-up model of non-collinear PNPN structures

Collin Reiman, Nathan Jack, Elyse Rosenbaum

Research output: Chapter in Book/Report/Conference proceedingConference contribution


A scalable I-V model for latch-up in non-collinear PNPN devices is adapted from a previous model for collinear SCR devices. The model is applied to 14-nm FinFET test structures. Layout scaling trends for key latch-up metrics, such as holding and trigger voltage, are captured by the model in circuit simulation. TCAD simulation is used to gain physical insight into the behavior of non-collinear PNPN devices.

Original languageEnglish (US)
Title of host publicationElectrical Overstress/Electrostatic Discharge Symposium Proceedings, EOS/ESD 2018
PublisherESD Association
ISBN (Electronic)1585373028
StatePublished - Oct 25 2018
Event40th Annual Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2018 - Reno, United States
Duration: Sep 23 2018Sep 28 2018

Publication series

NameElectrical Overstress/Electrostatic Discharge Symposium Proceedings
ISSN (Print)0739-5159


Other40th Annual Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2018
Country/TerritoryUnited States

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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