Large vector extensions inside the HMC

Marco A.Z. Alves, Matthias Diener, Paulo C. Santos, Luigi Carro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

One of the main challenges for embedded systems is the transfer of data between memory and processor. In this context, Hybrid Memory Cubes (HMCs) can provide substantial energy and bandwidth improvements compared to traditional memory organizations, while also allowing the execution of simple atomic instructions in the memory. However, the complex memory hierarchy still remains a bottleneck, especially for applications with a low reuse of data, limiting the usable parallelism of the HMC vaults and banks. In this paper, we introduce the HIVE architecture, which allows performing common vector operations directly inside the HMC, avoiding contention on the interconnections as well as cache pollution. Our mechanism achieves substantial speedups of up to 17.3× (9.4× on average) compared to a baseline system that performs vector operations in a 8-core processor. We show that the simple instructions provided by HMC actually hurt performance for streaming applications.

Original languageEnglish (US)
Title of host publicationProceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1249-1254
Number of pages6
ISBN (Electronic)9783981537062
StatePublished - Apr 25 2016
Externally publishedYes
Event19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016 - Dresden, Germany
Duration: Mar 14 2016Mar 18 2016

Publication series

NameProceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016

Other

Other19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
Country/TerritoryGermany
CityDresden
Period3/14/163/18/16

Keywords

  • HMC
  • Near-data processing
  • vector instructions

ASJC Scopus subject areas

  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality

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