L1 data cache decomposition for energy efficiency

M. Huang, J. Renau, S. M. Yoo, J. Torrellas

Research output: Contribution to conferencePaper

Abstract

The L1 data cache is a time-critical module and, at the same time, a major consumer of energy. To reduce its energy-delay product, we apply two principles of low-power design: specialize part of the cache structure and break the cache down into smaller caches. To this end, we propose a new L1 data cache structure that combines a Specialized Stack Cache (SSC) and a Pseudo Set-Associative Cache (PSAC). Individually, our SSC and PSAC designs have a lower energy-delay product than previously-proposed related designs. In addition, their combined operation is very effective. Relative to a conventional 2-way 32 KB data cache, a design containing a 4-way 32 KB PSAC and a 512 B SSC reduces the energy-delay product of several applications by an average of 44%.

Original languageEnglish (US)
Pages10-15
Number of pages6
DOIs
StatePublished - 2001
EventInternational Symposium on Low Electronics and Design (ISLPED'01) - Huntington Beach, CA, United States
Duration: Aug 6 2001Aug 7 2001

Other

OtherInternational Symposium on Low Electronics and Design (ISLPED'01)
CountryUnited States
CityHuntington Beach, CA
Period8/6/018/7/01

ASJC Scopus subject areas

  • Engineering(all)

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    Huang, M., Renau, J., Yoo, S. M., & Torrellas, J. (2001). L1 data cache decomposition for energy efficiency. 10-15. Paper presented at International Symposium on Low Electronics and Design (ISLPED'01), Huntington Beach, CA, United States. https://doi.org/10.1145/383082.383086