L1 data cache decomposition for energy efficiency

M. Huang, J. Renau, S. M. Yoo, Josep Torrellas

Research output: Contribution to conferencePaper

Abstract

The L1 data cache is a time-critical module and, at the same time, a major consumer of energy. To reduce its energy-delay product, we apply two principles of low-power design: specialize part of the cache structure and break the cache down into smaller caches. To this end, we propose a new L1 data cache structure that combines a Specialized Stack Cache (SSC) and a Pseudo Set-Associative Cache (PSAC). Individually, our SSC and PSAC designs have a lower energy-delay product than previously-proposed related designs. In addition, their combined operation is very effective. Relative to a conventional 2-way 32 KB data cache, a design containing a 4-way 32 KB PSAC and a 512 B SSC reduces the energy-delay product of several applications by an average of 44%.

Original languageEnglish (US)
Pages10-15
Number of pages6
StatePublished - Jan 1 2001
EventInternational Symposium on Low Electronics and Design (ISLPED'01) - Huntington Beach, CA, United States
Duration: Aug 6 2001Aug 7 2001

Other

OtherInternational Symposium on Low Electronics and Design (ISLPED'01)
CountryUnited States
CityHuntington Beach, CA
Period8/6/018/7/01

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Energy efficiency
Decomposition

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Huang, M., Renau, J., Yoo, S. M., & Torrellas, J. (2001). L1 data cache decomposition for energy efficiency. 10-15. Paper presented at International Symposium on Low Electronics and Design (ISLPED'01), Huntington Beach, CA, United States.

L1 data cache decomposition for energy efficiency. / Huang, M.; Renau, J.; Yoo, S. M.; Torrellas, Josep.

2001. 10-15 Paper presented at International Symposium on Low Electronics and Design (ISLPED'01), Huntington Beach, CA, United States.

Research output: Contribution to conferencePaper

Huang, M, Renau, J, Yoo, SM & Torrellas, J 2001, 'L1 data cache decomposition for energy efficiency' Paper presented at International Symposium on Low Electronics and Design (ISLPED'01), Huntington Beach, CA, United States, 8/6/01 - 8/7/01, pp. 10-15.
Huang M, Renau J, Yoo SM, Torrellas J. L1 data cache decomposition for energy efficiency. 2001. Paper presented at International Symposium on Low Electronics and Design (ISLPED'01), Huntington Beach, CA, United States.
Huang, M. ; Renau, J. ; Yoo, S. M. ; Torrellas, Josep. / L1 data cache decomposition for energy efficiency. Paper presented at International Symposium on Low Electronics and Design (ISLPED'01), Huntington Beach, CA, United States.6 p.
@conference{4a9dd917e8c44ed8abffbf0579d071da,
title = "L1 data cache decomposition for energy efficiency",
abstract = "The L1 data cache is a time-critical module and, at the same time, a major consumer of energy. To reduce its energy-delay product, we apply two principles of low-power design: specialize part of the cache structure and break the cache down into smaller caches. To this end, we propose a new L1 data cache structure that combines a Specialized Stack Cache (SSC) and a Pseudo Set-Associative Cache (PSAC). Individually, our SSC and PSAC designs have a lower energy-delay product than previously-proposed related designs. In addition, their combined operation is very effective. Relative to a conventional 2-way 32 KB data cache, a design containing a 4-way 32 KB PSAC and a 512 B SSC reduces the energy-delay product of several applications by an average of 44{\%}.",
author = "M. Huang and J. Renau and Yoo, {S. M.} and Josep Torrellas",
year = "2001",
month = "1",
day = "1",
language = "English (US)",
pages = "10--15",
note = "International Symposium on Low Electronics and Design (ISLPED'01) ; Conference date: 06-08-2001 Through 07-08-2001",

}

TY - CONF

T1 - L1 data cache decomposition for energy efficiency

AU - Huang, M.

AU - Renau, J.

AU - Yoo, S. M.

AU - Torrellas, Josep

PY - 2001/1/1

Y1 - 2001/1/1

N2 - The L1 data cache is a time-critical module and, at the same time, a major consumer of energy. To reduce its energy-delay product, we apply two principles of low-power design: specialize part of the cache structure and break the cache down into smaller caches. To this end, we propose a new L1 data cache structure that combines a Specialized Stack Cache (SSC) and a Pseudo Set-Associative Cache (PSAC). Individually, our SSC and PSAC designs have a lower energy-delay product than previously-proposed related designs. In addition, their combined operation is very effective. Relative to a conventional 2-way 32 KB data cache, a design containing a 4-way 32 KB PSAC and a 512 B SSC reduces the energy-delay product of several applications by an average of 44%.

AB - The L1 data cache is a time-critical module and, at the same time, a major consumer of energy. To reduce its energy-delay product, we apply two principles of low-power design: specialize part of the cache structure and break the cache down into smaller caches. To this end, we propose a new L1 data cache structure that combines a Specialized Stack Cache (SSC) and a Pseudo Set-Associative Cache (PSAC). Individually, our SSC and PSAC designs have a lower energy-delay product than previously-proposed related designs. In addition, their combined operation is very effective. Relative to a conventional 2-way 32 KB data cache, a design containing a 4-way 32 KB PSAC and a 512 B SSC reduces the energy-delay product of several applications by an average of 44%.

UR - http://www.scopus.com/inward/record.url?scp=0034863715&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034863715&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0034863715

SP - 10

EP - 15

ER -