Abstract
Problems of voiding and poor contact resistance have plagued recent attempts to apply salicide technology to silicon-on-insulator (S01) transistors. A physical picture is developed to explain why these problems occur. The picture rests on the known kinetics of silicide formation and the resistance to silicon diffusion imposed by device geometry.
Original language | English (US) |
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Pages (from-to) | L28-L30 |
Journal | Journal of the Electrochemical Society |
Volume | 142 |
Issue number | 2 |
DOIs | |
State | Published - Feb 1995 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Renewable Energy, Sustainability and the Environment
- Surfaces, Coatings and Films
- Electrochemistry
- Materials Chemistry