Abstract
In this paper we propose using joint equalization and coding to improve on-chip communication speeds by signaling at rates beyond the rate governed by RC delay of the interconnect. Operating beyond the RC limit introduces intersymbol interference (ISI). We mitigate the effects of ISI by employing equalization. The proposed equalizer employs a variable threshold inverter whose switching threshold is modified as a function of past output of the bus. We demonstrate even higher speed-ups by combining equalization with crosstalk avoidance coding. Specifically, simulation results for a 10-mm 32-bit bus in 0.13-/spl mu/m CMOS technology show that 1.28/spl times/ speed-up is achievable by equalization alone and 2.30/spl times/ speed-up is achievable by joint equalization and coding.
Original language | English (US) |
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Title of host publication | Proceedings - 6th International Symposium on Quality Electronic Design, ISQED 2005 |
Pages | 642-647 |
Number of pages | 6 |
DOIs | |
State | Published - 2005 |
Event | 6th International Symposium on Quality Electronic Design, ISQED 2005 - San Jose, CA, United States Duration: Mar 21 2005 → Mar 23 2005 |
Other
Other | 6th International Symposium on Quality Electronic Design, ISQED 2005 |
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Country | United States |
City | San Jose, CA |
Period | 3/21/05 → 3/23/05 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality