Joint equalization and coding for on-chip bus communication

Srinivasa R. Sridhara, Ganesh Balamurugan, Naresh R. Shanbhag

Research output: Contribution to journalArticlepeer-review


In this paper, we propose using joint equalization and coding to improve on-chip communication speeds by signaling at rates beyond the rate governed by resistance-capacitance (RC) delay of the interconnect. Operating beyond the RC limit introduces inter-symbol interference (ISI). We mitigate the effects of ISI by employing equalization. The proposed equalizer employs a variable threshold inverter whose switching threshold is modified as a function of past output of the bus. We demonstrate even higher speedups by combining equalization with crosstalk avoidance coding. Specifically, simulation results for a 10-mm 32-bit bus in 0.13-μm CMOS technology show that 1.28 × speedup is achievable by equalization alone and 2.30 × speedup is achievable by joint equalization and coding.

Original languageEnglish (US)
Article number4453957
Pages (from-to)314-318
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number3
StatePublished - Mar 2008


  • Coding
  • Crosstalk avoidance
  • Delay
  • Equalization
  • Interconnection networks
  • On-chip buses
  • System-on-chip (SOC)

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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