Jitter degrades the performance of both high-speed serial and parallel I/O links by limiting the maximum achievable data-rates. We present analytical expressions to evaluate the effect of jitter on the performance of high-speed links. These expressions enable simple calculation of worst-case voltage and timing margins in the presence of jitter. This analysis is also extended to equalized links. Finally, we show that the limited bandwidth of the channel can amplify high frequency jitter and present means to counteract jitter amplification.
|Original language||English (US)|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - Sep 6 2004|
|Event||2004 IEEE International Symposium on Circuits and Systems - Proceedings - Vancouver, BC, Canada|
Duration: May 23 2004 → May 26 2004
ASJC Scopus subject areas
- Electrical and Electronic Engineering