JIT trace-based verification for high-level synthesis

Liwei Yang, Magzhan Ikram, Swathi Gurumani, Suhaib Fahmy, Deming Chen, Kyle Rupnow

Research output: Chapter in Book/Report/Conference proceedingConference contribution


High level synthesis (HLS) tools are increasingly adopted for hardware design as the quality of tools consistently improves. Concerted development effort on HLS tools represents significant software development effort, and debugging and validation represents a significant portion of that effort. However, HLS tools are different from typical large-scale software systems; HLS tool output must be subsequently verified through functional verification of the generated RTL implementation. Debugging machine-generated functionally incorrect RTL is time-consuming and cumbersome requiring back-Tracing through hundreds of signals and simulation cycles to determine the underlying error. This challenging process requires support framework in the HLS flow to enable fast and efficient pinpointing of the incorrectness in the tool. In this paper, we present a debug framework that uses just-in-Time (JIT) traces and automated insertion of verification code into the generated RTL to assist in debugging an HLS tool. This framework aids the user by quickly pinpointing the earliest instance of execution mismatch, paired with detailed information on the faulty signal, and the corresponding instruction from the application source. Using CHStone benchmarks, we demonstrate that this technique can significantly reduce bug detection latency: often with zero cycle detection.

Original languageEnglish (US)
Title of host publication2015 International Conference on Field Programmable Technology, FPT 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)9781467390910
StatePublished - Jan 25 2016
EventInternational Conference on Field Programmable Technology, FPT 2015 - Queenstown, New Zealand
Duration: Dec 7 2015Dec 9 2015

Publication series

Name2015 International Conference on Field Programmable Technology, FPT 2015


OtherInternational Conference on Field Programmable Technology, FPT 2015
Country/TerritoryNew Zealand


  • High-Level Synthesis
  • JIT
  • Trace-based Verification

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture
  • Software


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