TY - GEN
T1 - Invited
T2 - 59th ACM/IEEE Design Automation Conference, DAC 2022
AU - Ye, Hanchen
AU - Jun, Hye Gang
AU - Jeong, Hyunmin
AU - Neuendorffer, Stephen
AU - Chen, Deming
N1 - Funding Information:
4 CONCLUSION AND FUTURE WORKS In this paper, we introduce a ScaleHLS framework with multi-levels of IR and scalable support on the optimization of HLS designs. We propose an HLS-dedicated transform and analysis library in both C++ and Python that improves the modularity of the framework. A hierarchical DSE algorithm is proposed, which achieves promising speedup on a set of benchmarks from PolyBench and Rosetta. Several directions are left as future works: 1) Memory management. The on-chip and off-chip memory resources are supposed to be carefully managed in order to achieve the best computing efficiency. 2) Hierarchical dataflow. Dataflow optimization is essential for multi-kernel HLS designs to enable the spatial parallelism and improve the throughput. 3) RTL generation. We are working on the integration of ScaleHLS and CIRCT [2] aiming to directly generate optimized RTL designs from MLIR. 4) IP integration. We can leverage existing highly-optimized IPs to reduce the size of design spaces to explore and improve the quality of generated designs. ACKNOWLEDGMENTS This work is supported in part by Xilinx Center of Excellence at UIUC, Xilinx Adaptive Compute Cluster (XACC) initiative, and BAH HT 15-1158 contract. REFERENCES
Publisher Copyright:
© 2022 ACM.
PY - 2022/7/10
Y1 - 2022/7/10
N2 - This paper presents an enhanced version of a scalable HLS (High-Level Synthesis) framework named ScaleHLS, which can compile HLS C/C++ programs and PyTorch models to highly-efficient and synthesizable C++ designs. The original version of ScaleHLS achieved significant speedup on both C/C++ kernels and PyTorch models [14]. In this paper, we first highlight the key features of ScaleHLS on tackling the challenges present in the representation, optimization, and exploration of large-scale HLS designs. To further improve the scalability of ScaleHLS, we then propose an enhanced HLS transform and analysis library supported in both C++ and Python, and a new design space exploration algorithm to handle HLS designs with hierarchical structures more effectively. Comparing to the original ScaleHLS, our enhanced version improves the speedup by up to 60.9× on FPGAs. ScaleHLS is fully open-sourced at https://github.com/hanchenye/scalehls.
AB - This paper presents an enhanced version of a scalable HLS (High-Level Synthesis) framework named ScaleHLS, which can compile HLS C/C++ programs and PyTorch models to highly-efficient and synthesizable C++ designs. The original version of ScaleHLS achieved significant speedup on both C/C++ kernels and PyTorch models [14]. In this paper, we first highlight the key features of ScaleHLS on tackling the challenges present in the representation, optimization, and exploration of large-scale HLS designs. To further improve the scalability of ScaleHLS, we then propose an enhanced HLS transform and analysis library supported in both C++ and Python, and a new design space exploration algorithm to handle HLS designs with hierarchical structures more effectively. Comparing to the original ScaleHLS, our enhanced version improves the speedup by up to 60.9× on FPGAs. ScaleHLS is fully open-sourced at https://github.com/hanchenye/scalehls.
UR - http://www.scopus.com/inward/record.url?scp=85137493716&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85137493716&partnerID=8YFLogxK
U2 - 10.1145/3489517.3530631
DO - 10.1145/3489517.3530631
M3 - Conference contribution
AN - SCOPUS:85137493716
T3 - Proceedings - Design Automation Conference
SP - 1355
EP - 1358
BT - Proceedings of the 59th ACM/IEEE Design Automation Conference, DAC 2022
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 10 July 2022 through 14 July 2022
ER -