TY - GEN
T1 - Invited
T2 - 61st ACM/IEEE Design Automation Conference, DAC 2024
AU - Huang, Yingbing
AU - Wan, Lily Jiaxin
AU - Ye, Hanchen
AU - Jha, Manvi
AU - Wang, Jinghua
AU - Li, Yuhong
AU - Zhang, Xiaofan
AU - Chen, Deming
N1 - This work is supported in part by the IBM-Illinois Discovery Accelerator Institute, AMD Center of Excellence at UIUC, AMD Heterogeneous Adaptive Compute Cluster (HACC) initiative, NSF 2117997 grant through the A3D3 institute, and Semiconductor Research Corporation (SRC) 2023-CT-3175 grant.
PY - 2024/11/7
Y1 - 2024/11/7
N2 - Large Language Models (LLMs) have revolutionized a wide range of applications with their strong human-like understanding and creativity. Due to the continuously growing model size and complexity, LLM training and deployment have shown significant challenges, which often results in extremely high computational and storage costs and energy consumption. In this paper, we discuss the recent advancements and research directions on (1) LLM algorithm-level acceleration, (2) LLM-hardware co-design for improved system efficiency, (3) LLM-to-accelerator compilation for customized LLM accelerators, and (4) LLM-aided design for HLS (High-Level Synthesis) functional verification. For each aspect, we present the background study, our proposed solutions, and future directions. An extended version of this work can be found at: https://arxiv.org/abs/2406.10903.
AB - Large Language Models (LLMs) have revolutionized a wide range of applications with their strong human-like understanding and creativity. Due to the continuously growing model size and complexity, LLM training and deployment have shown significant challenges, which often results in extremely high computational and storage costs and energy consumption. In this paper, we discuss the recent advancements and research directions on (1) LLM algorithm-level acceleration, (2) LLM-hardware co-design for improved system efficiency, (3) LLM-to-accelerator compilation for customized LLM accelerators, and (4) LLM-aided design for HLS (High-Level Synthesis) functional verification. For each aspect, we present the background study, our proposed solutions, and future directions. An extended version of this work can be found at: https://arxiv.org/abs/2406.10903.
KW - Acceleration
KW - Functional Verification
KW - Hardware Design
KW - High-Level Synthesis (HLS)
KW - Large Language Models (LLMs)
UR - http://www.scopus.com/inward/record.url?scp=85211094378&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85211094378&partnerID=8YFLogxK
U2 - 10.1145/3649329.3663517
DO - 10.1145/3649329.3663517
M3 - Conference contribution
AN - SCOPUS:85211094378
T3 - Proceedings - Design Automation Conference
BT - Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 23 June 2024 through 27 June 2024
ER -