TY - GEN
T1 - Investigation of current flow during wafer-level CDM using real-time probing
AU - Jack, Nathan
AU - Shukla, Vrashank
AU - Rosenbaum, Elyse
PY - 2010/12/24
Y1 - 2010/12/24
N2 - Using real-time voltage probing and circuit simulation, the stress induced by wafer-level CDM test methods is compared to that of package-level FICDM testers. It is shown that while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the induced current stress.
AB - Using real-time voltage probing and circuit simulation, the stress induced by wafer-level CDM test methods is compared to that of package-level FICDM testers. It is shown that while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the induced current stress.
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M3 - Conference contribution
AN - SCOPUS:78650353895
SN - 1585371823
SN - 9781585371822
T3 - Electrical Overstress/Electrostatic Discharge Symposium Proceedings
BT - Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010, EOS/ESD 2010
T2 - 32nd Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2010
Y2 - 3 October 2010 through 8 October 2010
ER -