Investigation of current flow during wafer-level CDM using real-time probing

Nathan Jack, Vrashank Shukla, Elyse Rosenbaum

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Using real-time voltage probing and circuit simulation, the stress induced by wafer-level CDM test methods is compared to that of package-level FICDM testers. It is shown that while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the induced current stress.

Original languageEnglish (US)
Title of host publicationElectrical Overstress/Electrostatic Discharge Symposium Proceedings 2010, EOS/ESD 2010
StatePublished - Dec 24 2010
Event32nd Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2010 - Reno, NV, United States
Duration: Oct 3 2010Oct 8 2010

Publication series

NameElectrical Overstress/Electrostatic Discharge Symposium Proceedings
ISSN (Print)0739-5159

Other

Other32nd Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2010
CountryUnited States
CityReno, NV
Period10/3/1010/8/10

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Jack, N., Shukla, V., & Rosenbaum, E. (2010). Investigation of current flow during wafer-level CDM using real-time probing. In Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010, EOS/ESD 2010 [5623758] (Electrical Overstress/Electrostatic Discharge Symposium Proceedings).