Inverse polarity techniques for high-speed/low-power multipliers

Pascal C.H. Meier, Robin A Rutenbar, L. Richard Carley

Research output: Contribution to conferencePaper

Abstract

Various high-speed techniques have been developed for multipliers, but with the increasing popularity of mobile computing, a recent goal has been to minimize power dissipation. A popular delay-reduction technique applied to adder circuits is polarity inversion of bits. As this optimization reduces transistor count, it also has the potential for lowering power dissipation, and can be effectively applied to Wallace tree partial product reduction stages. We illustrate how this technique reduces power, interconnect capacitance, and chip area. Power reduction of up to 25% is achieved.

Original languageEnglish (US)
Pages264-266
Number of pages3
StatePublished - Dec 1 1999
EventProceedings of the 1999 International Conference on Low Power Electronics and Design (ISLPED) - San Diego, CA, USA
Duration: Aug 16 1999Aug 17 1999

Conference

ConferenceProceedings of the 1999 International Conference on Low Power Electronics and Design (ISLPED)
CitySan Diego, CA, USA
Period8/16/998/17/99

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Meier, P. C. H., Rutenbar, R. A., & Carley, L. R. (1999). Inverse polarity techniques for high-speed/low-power multipliers. 264-266. Paper presented at Proceedings of the 1999 International Conference on Low Power Electronics and Design (ISLPED), San Diego, CA, USA, .