Introduction to nanotechnology

Deming Chen, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceedingForeword/postscript


The semiconductor industry has showcased a spectacular exponential growth in the number of transistors per integrated circuit for several decades, as predicted by Moore's law. Figure 1 shows the future technology trend predicted by ITRS (International Technology Roadmap for Semiconductors) [1]. By 2023, the physical gate length would scale down to 4.5 nm. Actually, according to a study [2], future devices could theoretically scale down to 1.5 nm with 0.04 ps switching speed and 0.017 eV energy consumption. However, maintaining such an exponential growth rate is a major challenge. Physical dimensions and electrostatic limitations faced by conventional process and fabrication technologies will likely thwart the dimensional scaling of complementary metal-oxide-semiconductor (CMOS) devices within the next decade. Figure 2 from ITRS shows that after 2016, the manufacturable solutions are unknown (the shaded area).

Original languageEnglish (US)
Title of host publicationNanoelectronic Circuit Design
Number of pages22
ISBN (Print)9781441974440
StatePublished - 2011

ASJC Scopus subject areas

  • General Engineering


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