Interconnections in multi-core architectures: Understanding mechanisms, overheads and scaling

Rakesh Kumar, Victor Zyuban, Dean M. Tullsen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class of interconnect architectures. It shows that the design choices for the interconnect have significant effect on the rest of the chip, potentially consuming a significant fraction of the real estate and power budget. This research shows that designs that treat interconnect as an entity that can be independently architected and optimized would not arrive at the best multicore design. Several examples are presented showing the need for careful co-design. For instance, increasing interconnect bandwidth requires area that then constrains the number of corim or cache sizes, and does not necessarily increase performance. Also, shared level-2 caches become significantly less attractive when the overhead of the resulting crossbar is accounted for. A hierarchical bus structure is examined which negates some of the performance costs of the assumed base-line architecture.

Original languageEnglish (US)
Title of host publicationProceedings - 32nd International Symposium on Computer Architecture, ISCA 2005
Pages408-419
Number of pages12
DOIs
StatePublished - 2005
Externally publishedYes
Event32nd Interntional Symposium on Computer Architecture, ISCA 2005 - Madison, WI, United States
Duration: Jun 4 2005Jun 8 2005

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897

Other

Other32nd Interntional Symposium on Computer Architecture, ISCA 2005
CountryUnited States
CityMadison, WI
Period6/4/056/8/05

ASJC Scopus subject areas

  • Engineering(all)

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