Interconnect transient simulation in the presence of layout and routing uncertainty

Aosheng Rong; Andreas C. Cangellaris

doi:10.1109/EPEPS.2011.6100214

Interconnect transient simulation in the presence of layout and routing uncertainty

Aosheng Rong, Andreas C. Cangellaris

Coordinated Science Lab

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A methodology is presented for the calculation of the transient transmission-line response of package-level or board-level interconnects in the presence of layout and routing uncertainty. The proposed methodology makes use of the generalized polynomial chaos framework and advances in sparse stochastic collocation for interpolation and sampling in the probability space defined by the random variables that describe routing uncertainty. In this manner, a modeling framework is established that facilitates the computation of the statistics of the transient response and its post-processing for the purpose of assessing the impact of interconnect layout and routing uncertainty on signal distortion and crosstalk.

Original language	English (US)
Title of host publication	2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011
Pages	157-160
Number of pages	4
DOIs	https://doi.org/10.1109/EPEPS.2011.6100214
State	Published - 2011
Event	2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011 - San Jose, CA, United States Duration: Oct 23 2011 → Oct 26 2011

Publication series

Name	2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011

Other

Other	2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011
Country/Territory	United States
City	San Jose, CA
Period	10/23/11 → 10/26/11

Keywords

interconnects
signal integrity
stochastic modeling

ASJC Scopus subject areas

Electrical and Electronic Engineering

Online availability

10.1109/EPEPS.2011.6100214

Library availability

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Rong, A., & Cangellaris, A. C. (2011). Interconnect transient simulation in the presence of layout and routing uncertainty. In 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011 (pp. 157-160). Article 6100214 (2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011). https://doi.org/10.1109/EPEPS.2011.6100214

Interconnect transient simulation in the presence of layout and routing uncertainty. / Rong, Aosheng; Cangellaris, Andreas C.
2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011. 2011. p. 157-160 6100214 (2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Rong, A & Cangellaris, AC 2011, Interconnect transient simulation in the presence of layout and routing uncertainty. in 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011., 6100214, 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011, pp. 157-160, 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011, San Jose, CA, United States, 10/23/11. https://doi.org/10.1109/EPEPS.2011.6100214

Rong A, Cangellaris AC. Interconnect transient simulation in the presence of layout and routing uncertainty. In 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011. 2011. p. 157-160. 6100214. (2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011). doi: 10.1109/EPEPS.2011.6100214

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Interconnect transient simulation in the presence of layout and routing uncertainty

Abstract

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Other

Keywords

ASJC Scopus subject areas

Online availability

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