Interconnect transient simulation in the presence of layout and routing uncertainty

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A methodology is presented for the calculation of the transient transmission-line response of package-level or board-level interconnects in the presence of layout and routing uncertainty. The proposed methodology makes use of the generalized polynomial chaos framework and advances in sparse stochastic collocation for interpolation and sampling in the probability space defined by the random variables that describe routing uncertainty. In this manner, a modeling framework is established that facilitates the computation of the statistics of the transient response and its post-processing for the purpose of assessing the impact of interconnect layout and routing uncertainty on signal distortion and crosstalk.

Original languageEnglish (US)
Title of host publication2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011
Pages157-160
Number of pages4
DOIs
StatePublished - Dec 1 2011
Event2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011 - San Jose, CA, United States
Duration: Oct 23 2011Oct 26 2011

Publication series

Name2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011

Other

Other2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011
CountryUnited States
CitySan Jose, CA
Period10/23/1110/26/11

Keywords

  • interconnects
  • signal integrity
  • stochastic modeling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Rong, A., & Cangellaris, A. C. (2011). Interconnect transient simulation in the presence of layout and routing uncertainty. In 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011 (pp. 157-160). [6100214] (2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011). https://doi.org/10.1109/EPEPS.2011.6100214